参数资料
型号: QL8150-6PT280I
厂商: QUICKLOGIC CORP
元件分类: FPGA
英文描述: FPGA, 640 CLBS, 188946 GATES, PBGA280
封装: 0.80 MM PITCH, LFBGA-280
文件页数: 56/96页
文件大小: 1607K
代理商: QL8150-6PT280I
2007 QuickLogic Corporation
Eclipse II Family Data Sheet Rev. Q
6
Figure 5: ECU Block Diagram
The Eclipse II ECU blocks (Table 4) are placed next to the SRAM circuitry for efficient memory/instruction
fetch and addressing for DSP algorithmic implementations.
Up to twelve 8-bit MAC functions can be implemented per cycle for a total of 1 billion MACs/s when clocked
at 100 MHz. Additional multiply-accumulate functions can be implemented in the programmable logic.
The modes for the ECU block are dynamically re-programmable through the programmable logic.
Table 4: Eclipse II ECU Blocks
Device
ECUs
QL8325
12
QL8250
10
QL8150
0
QL8050
0
QL8025
0
A[0:15]
B[0:15]
SIGN2
SIGN1
CIN
S1
S2
S3
A
B
C
D
3-4
decoder
8-bit
Multiplier
16-bit
Adder
17-bit
Register
2-1
mux
2-1
mux
3-1
mux
Q[16:0]
CLK
RESET
DQ
00
01
10
A[7:0]
A[15:8]
相关PDF资料
PDF描述
QL8150-6PT280M FPGA, 640 CLBS, 188946 GATES, PBGA280
QL8150-6PTN280C FPGA, 640 CLBS, 188946 GATES, PBGA280
QL8150-6PTN280I FPGA, 640 CLBS, 188946 GATES, PBGA280
QL8150-6PTN280M FPGA, 640 CLBS, 188946 GATES, PBGA280
QL8150-6PUN196C FPGA, 640 CLBS, 188946 GATES, PBGA196
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