参数资料
型号: RTPXA270C0C312
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 312 MHz, RISC PROCESSOR, PBGA356
封装: 13 X 13 MM, 1 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, VFBGA-356
文件页数: 102/128页
文件大小: 1560K
代理商: RTPXA270C0C312
Electrical, Mechanical, and Thermal Specification
6-11
Intel PXA270 Processor
AC Timing Specifications
6.2.10
Voltage-Change Timing
The PWR I2C uses the regular I2C protocol. The PWR I2C is clocked at 40 kHz (160 kHz fast-
mode operation is supported). Software controls the time required for initiating the voltage change
sequence through completion. The voltage-change timing is a product of the number of commands
issued plus the number of software programmed delays. Table 6-12 shows the timing of a 1 byte
command issued to the power manager IC.
Set the I2C programmable output ramp rate with a default/reset ramp rate of 10mV/
s (refer to
VCC_CORE ramp rate specification in the Electrical Section) to support VCC_CORE dynamic
voltage management.
Table 6-12. Voltage-Change Timing Specification for a 1-Byte Command
6.3
GPIO Timing Specifications
Table 6-13 shows the general-purpose I/O (GPIO) AC timing specifications.
Symbol
Description
Min
Typical
Max
Units
Delay between voltage change sequence
start1 to command received by PMIC
18
cycles2
NOTES:
1. Write 1 to PWRMODE[VC]
2. 40 kHz cycles
Table 6-13. GPIO Timing Specifications
Symbol
Parameter
Min
Max
Units
Notes
taGPIO1
Assertion time required to detect
GPIO edge
154
ns
run, idle, or sense power modes
taGPIOLP2
Assertion time required to detect
GPIO low-power edge
62.5
s
standby, sleep, or deep-sleep
power modes
tdGPIO1
De-assertion time required to
detect GPIO edge
154
ns
run, idle, or sense power modes
tdGPIOLP2
De-assertion time required to
detect GPIO low-power edge
62.5
s
standby, sleep, or deep-sleep
power modes
tdiGPIO3
Time it takes for a GPIO edge to
be detected internally
231
ns
run, idle, or sense power modes
tdiGPIOLP4
Time it takes for a GPIO low-
power edge to be detected
internally
93.75
s
standby, sleep, or deep-sleep
power modes
NOTES:
1. Period equal to two 13-MHz cycles
2. Period equal to two 32-kHz cycles
3. Period equal to three 13-MHz cycles
4. Period equal to three 32-kHz cycles
Note 4 describes the complete timing for a standby, sleep, or deep-sleep wake up source to be asserted and detected internally
(2 cycles for assertion (note 2) and 1 additional cycle for detection).
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