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参数资料
| 型号： | SLC88B17QFP |
| 厂商： | STANDARD MICROSYSTEMS CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | ISA BUS CONTROLLER, PQFP160 |
| 封装： | QFP-160 |
| 文件页数： | 11/54页 |
| 文件大小： | 333K |
| 代理商： | SLC88B17QFP |
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SMSC DS – SLC88B17
Page 19
Rev. 09/28/99
PCI/ISA BRIDGE FUNCTIONAL DESCRIPTION
This section describes the major functions of the SLC88B17 PCI-to-ISA bridge.
Memory Map
The SLC88B17 interfaces to two system buses: PCI and ISA buses. The SLC88B17 normally acts as a subtractive
decoding agent. It also provides positive decode for certain memory space accesses on the PCI bus. ISA masters
and DMA devices can access PCI memory. ISA masters and DMA devices do not have accesses to host or PCI I/O
space.
ISA/DMA Memory Access
The following table shows the SLC88B17’s action when ISA Master or DMA accesses to the memory space.
MEMORY ADDRESS RANGE OF
A DMA/ISA MASTER CYCLE
ACTION
(Top of Memory) to 128 Mbyte
Confine to ISA
1Mbyte to (Top of Memory)
Forward to PCI. Top of Memory is declared
via bits 7-4 of TOM.
(1Mbyte – 64Kbyte) to 1Mbyte
Forward to PCI
(1Mbyte - 128Kbyte) to (1Mbyte -64Kbyte)
Forward to PCI if bit3/TOM=1
768Kbyte to (1Mbyte - 128Kbyte)
Forward to PCI
640Kbyte to 768Kbyte
Forward to PCI if bit2/TOM =1
512Kbyte to 640Kbyte
Forward to PCI if bit1/TOM=1
0-512Kbyte
Forward to PCI
PC/PCI DMA Logic
PC/PCI DMA uses dedicated nISAREQ and nISAGNT signals to permit PCI devices to request transfers associated
with specific DMA channels. Upon receiving a request and getting control of the PCI bus, the south bridge asserts the
nISAGNT signal and performs a two-cycle transfer. For example, if data is to be moved from the peripheral to main
memory, the south bridge will first read data from the peripheral and then write it to main memory. The read-from-
peripheral cycle will then pass to ISA bus through the SLC88B17. The location in main memory is the Current
Address Registers in the DMA controller.
The SLC88B17 provides support for DMA across PCI using the PC/PCI DMA Protocol through the nISAREQ and
nISAGNT signal pair. The nISAREQ/nISAGNT pair follows the PC/PCI serial protocol described below.
FIGURE 4 - DMA SERIAL CHANNEL PASSING
The SLC88B17 encodes the channel request information as shown above, where CH0-CH7 are one clock active high
states representing DMA channel requests 0-7.
The south bridge encodes the granted channel on the nISAGNT line as shown above, where the bits have the same
meaning as shown in the figure. For example, the sequence [start, bit 0, bit 1, bit 2]=[0,1,0,0] grants DMA channel 1
to the SLC88B17, and the sequence [start, bit 0, bit 1, bit 2]=[0,0,1,1,] grants DMA channel 6 to the SLC88B17.
The SLC88B17 uses the channel passing protocol described above. It works as follows:
1.
If the SLC88B17 has more than one request active, it will resend the request serial protocol after one of the
requests has been granted the bus and it has completed its transfer. The SLC88B17 will drive its nISAREQ
inactive for two clocks and then transmit the serial channel passing protocol again, even if there are no new
nREQ
PCICLK
nGNT
Start
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
Start
Bit0
Bit1
Bit2
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相关代理商/技术参数 |
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