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参数资料
| 型号： | SLC88B17QFP |
| 厂商： | STANDARD MICROSYSTEMS CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | ISA BUS CONTROLLER, PQFP160 |
| 封装： | QFP-160 |
| 文件页数： | 8/54页 |
| 文件大小： | 333K |
| 代理商： | SLC88B17QFP |
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SMSC DS – SLC88B17
Page 16
Rev. 09/28/99
PCISTS
PCI Status Register
Offset Address:
06 - 07h
Default Value:
0200h
Access:
Read/Write
This register status information for PCI bus related events. Reads to this register behave normally. Bits in this register
can only be set by SLC88B17 events (through hardware)
BIT
FUNCTION
15
Detected Parity Error. Not implemented, hardwired to a 0.
14
Signaled nSERR Status. When the SLC88B17 asserts the nSERR signal, this bit is set to
1. Software can set this bit to a 0 by writing a 1 to it.
13
Master Abort Status. When the SLC88B17, as a master on the PCI bus, generates a
master abort, this bit is set to 1. Software can set this bit 0 by writing a 1 to it.
12
Received Target Abort Status. This bit is set when the SLC88B17 target aborts a PCI
transaction as a target. Software can set this bit 0 by writing a 1 to it.
11
Signaled Target Abort. This bit is set when the SLC88B17 signals a target abort for a
PCI transaction. Software can set this bit 0 by writing a 1 to it.
10-9
nDEVSEL Timing. Always 01 to select “medium” timing, which is two PCI clocks after the
assertion of nFRAME, when the SLC88B17 asserts nDEVSEL as a PCI target. The
medium timing is used for all positive decoding.
The SLC88B17 also does a medium
decode for PCI configuration accesses.
8
Parity Detected. Always 0, does not check parity.
7
Fast Back-to-Back. Always 0, does not support fast back-to-back transaction.
6
66 MHz/33MHz. Hardwired to 0. Maximum PCI bus frequency is 33MHz.
5
User Definable Features (UDF). Hardwired to 0. SLC88B17 does not support any UDFs.
4-0
Reserved.
RID
Revision Identification Register
Offset Address:
08h
Default Value:
00h
Access:
Read Only
BIT
FUNCTION
7-0
Hardwired to the revision number, which is set to 00 as the initial number.
CLASSCODE
Class Code Register
Offset Address:
09 - 0Bh
Default Value:
060100h
Access:
Read Only
This class code register is a read-only register used to identify SLC88B17. Writes to this register have no effect.
BIT
FUNCTION
23-16
Base Class Code. Always 06 indicating that the SLC88B17 is a bridge device.
15-8
Sub-Class Code. PCI-to-ISA subtractive decode bridge = 01h
7-0
Programming Interface. 00, no interface is defined.
HEDT
Header Type Register
Offset Address:
0Eh
Default Value:
00h
Access:
Read Only
This register is used to indicate that SLC88B17 configuration space adheres to PCI local bus specification. It also
indicates that SLC88B17 is not a multifunction device.
BIT
FUNCTION
7
Multifunction Indicator. 00h= not a multi-function device.
6-0
Layout Code. Value=0 (PCI layout type 00)
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