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参数资料
| 型号： | SLC88B17QFP |
| 厂商： | STANDARD MICROSYSTEMS CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | ISA BUS CONTROLLER, PQFP160 |
| 封装： | QFP-160 |
| 文件页数： | 7/54页 |
| 文件大小： | 333K |
| 代理商： | SLC88B17QFP |
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SMSC DS – SLC88B17
Page 15
Rev. 09/28/99
MISA Specific Register Mapping Table
OFFSET
ADDRESS
MNEMONIC
REGISTER NAME
ACCESS
RIGHT
42
MISA_STS
MISA Error Status Register
RO
43
TOM
Top of Memory Register
R/W
44-FF
Reserved
PCI/ISA Bridge PCI Register Description (Function 0)
This section describes in detail the registers associated with the SLC88B17 PCI-to-ISA bridge function.
VID
Vendor Identification Register
Offset Address:
00 - 01h
Default Value:
10B8h
Access:
Read Only
This is a 16 bit PCI Vendor ID assigned to SMSC.
DID
Device Identification Register
Offset Address:
02 - 03h
Default Value:
8170h
Access:
Read Only
This is the PCI device ID of the SLC88B17.
PCICMD
PCI Command Register
Offset Address:
04 - 05h
Default Value:
0007h
Access:
Read/Write
This register provides basic control over the SLC88B17’s ability to respond to PCI cycles. When a 0 is written to this
register, SLC88B17 is logically disconnected from the PCI bus for all accesses except configuration accesses.
BIT
FUNCTION
15-10
Reserved.
9
Fast Back-to-Back. Not implemented, hardwired to 0..
8
nSERR Enable: 1=Enable, 0=Disable. Controls the enable for the nSERR driver on the
PCI interface.
7-5
Reserved. Read as 0
4
Postable Memory Write Enable. This bit is hardwired to 0.
3
Special Cycle Enable. Not implemented, hardwired to 0.
2
Bus Master Enable. This bit is hardwired to a 1 (always enabled).
1
Memory Access Enable. The SLC88B17 memory Space is always enabled.. This bit is
hardwired to a 1.
0
IO Access Enable. The SLC88B17 I/O space is always enabled. This bit is hardwired to
a 1.
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