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参数资料
| 型号： | SLC88B17QFP |
| 厂商： | STANDARD MICROSYSTEMS CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | ISA BUS CONTROLLER, PQFP160 |
| 封装： | QFP-160 |
| 文件页数： | 15/54页 |
| 文件大小： | 333K |
| 代理商： | SLC88B17QFP |
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SMSC DS – SLC88B17
Page 22
Rev. 09/28/99
SERIAL INTERRUPTS
The SLC88B17 supports the serial interrupt to transmit interrupt requests to the host system. The serial interrupt
scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0.
Timing Diagrams For IRQSER Cycle
PCICLK = 33MHz_IN pin
IRQSER = SERIRQ pin
A)
Start Frame timing with source sampled a low pulse on IRQ1
RT
S
RT
S
IRQSER
PCICLK
Host Controller
IRQ1
Drive Source
RT
None
IRQ0 FRAME
IRQ1 FRAME
S
RT
IRQ2 FRAME
None
START
START FRAME
H
SL
or
H
1
H=Host Control
R=Recovery
S=Sample
SL=Slave Control
T=Turn-around
B)
Stop Frame Timing with Host using 17 IRQSER sampling period
S
RT
S
IRQSER
PCICLK
Host Controller
IRQ15
Driver
RT
None
IRQ14
IRQ15
S
RT
IOCHCK#
None
STOP
RT
STOP FRAME
H
I
START
NEXT CYCLE
1
2
3
FRAME
H=Host Control
T=Turn-around
I= Idle.
R=Recovery
S=Sample
1.
Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
2.
There may be none, one or more Idle states during the Stop Frame.
3.
The next IRQSER cycle’s Start Frame pulse may or may not start immediately after the turn-around clock of the
Stop Frame.
IRQSER Cycle Control
There are two modes of operation for the IRQSER Start Frame.
1) Quiet (Active) Mode: Any device may initiate a Start Frame by driving the IRQSER low for one clock, while the
IRQSER is Idle. After driving low for one clock the IRQSER must immediately be tri-stated without at any time driving
high. A Start Frame may not be initiated while the IRQSER is Active. The IRQSER is Idle between Stop and Start
Frames. The IRQSER is Active between Start and Stop Frames. This mode of operation allows the IRQSER to be
Idle when there are no IRQ/Data transitions which should be most of the time.
Once a Start Frame has been initiated the Host Controller will take over driving the IRQSER low in the next clock and
will continue driving the IRQSER low for a programmable period of three to seven clocks. This makes a total low
pulse width of four to eight clocks. Finally, the Host Controller will drive the IRQSER back high for one clock, then tri-
state.
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