SMSC DS – SLC88B17
Page 13
Rev. 09/28/99
Interrupt Signals
NAME
TYPE
DESCRIPTION
IRQ[3-7, 9-
11, 14-15]
I
Interrupt Requests. These interrupts may be programmed for either an edge
sensitive or a high level sensitive mode. Default is edge sensitive mode. If the
request goes inactive before it is acknowledged, a default IRQ7 is reported in
response to the interrupt acknowledge cycle.
IRQ12/M
I
Interrupt Request 12. This is an interrupt request channel 12. In addition, this pin
can also be programmed to provide the mouse interrupt function.
When the mouse interrupt is selected, the SLC88B17 latches a low to high transition
on this signal and generates an INTR to the CPU as IRQ12. An internal IRQ12
interrupt will continue to be generated until a Reset or an I/O read access to address
60h is detected.
SERIRQ
I/O
Serial Interrupt Request.
Serial interrupt request is used to transmit interrupt
requests to the host system.
Clocks
NAME
TYPE
DESCRIPTION
PCICLK
I
PCI Clock. This is a clock signal provides timing for all transactions on the PCI bus.
All other PCI signals are sampled on the rising edge of PCICLK, and all timing
parameters are defined with respect to the edge.
SYSCLK
O
ISA System Clock. SYSCLK is the reference clock for the ISA bus. It drives the ISA
bus directly. The SYSCLK is derived by dividing PCICLK by 4.
During Reset: Running
After Reset: Running
Mobile PCI-PCI
NAME
TYPE
DESCRIPTION
NOGO
I
NO GO. This signal indicates which master initiated the current transaction and also
indicates whether or not the current bus cycle is targeted for the ISA bus. This signal
is point–to-point connection between the PCI to PCI and SLC88B17.
Power and Ground Signals
NAME
TYPE
DESCRIPTION
VCC
V
Main Voltage Supply. These pins are the primary voltage supply for the SLC88B17
and must be tied to 5V.
VSS
V
Main Ground. These pins are the primary ground for the SLC88B17.
nTESTIN
I
Test Input. This signal should always be high.