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参数资料
| 型号： | SLC88B17QFP |
| 厂商： | STANDARD MICROSYSTEMS CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | ISA BUS CONTROLLER, PQFP160 |
| 封装： | QFP-160 |
| 文件页数： | 13/54页 |
| 文件大小： | 333K |
| 代理商： | SLC88B17QFP |
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SMSC DS – SLC88B17
Page 20
Rev. 09/28/99
requests from the PCI expansion agent to the south bridge. For example: If the SLC88B17 had active requests
for DMA channel 1 and Channel 5, it would pass this information to the south bridge through the expansion
channel passing protocol. If after receiving nISAGNT (assume for CH5) and having the device finish its transfer
(device stops driving request to the SLC88B17) it would then re-transmit the expansion channel passing protocol
to inform the south bridge that DMA channel 1 was still requesting the bus, even if that was the only request the
SLC88B17 had pending.
2.
If the SLC88B17 has a request go inactive before the south bridge asserts nISAGNT, it will resend the expansion
channel passing protocol to update the south bridge with this new request information. For example: if the
SLC88B17 has DMA channel 1 and 2 requests pending it will send them serially to the south bridge using the
expansion channel passing protocol. If, however, DMA channel 1 goes inactive into the SLC88B17 before the
SLC88B17 receives a nISAGNT from the south bridge, the SLC88B17 will pull its nISAREQ line high for one
clock and resend the expansion channel passing information with only DMA channel 2 active. Note that the
south bridge does not do anything special to catch this case because a DREQ going inactive before a nDACK is
received is not allowed in the ISA DMA protocol and, therefore, does not need to work properly in this protocol
either.
This requirement is needed to be able to support Plug-n-Play devices that toggle nDREQ lines to
determine if those lines are free in the system.
3.
If the SLC88B17 has sent its serial request information and receives a new DMA request before receiving
nISAGNT the SLC88B17 will resend the serial request with the new request active.
For example: if the
SLC88B17 has already passed requests for DMA channel 1 and 2 and sees DREQ 3 active before a nISAGNT is
received, it will pull its nREQ line high for one clock and resend the expansion channel passing information with
all three channels active.
The three cases above show the following functionality in the SLC88B17:
1.
Drive nISAREQ inactive for one clock to signal new request information.
2.
Drive nISAREQ inactive for two clocks to signal that a request that had been granted the bus has gone
inactive.
3.
The nISAREQ and nISAGNT state machines run independently and concurrently (i.e., a nISAGNT could be
received while in the middle of sending a serial nISAREQ or nISAGNT could be active while nISAREQ is
inactive).
PCI DMA Expansion Cycles
In the PC/PCI DMA mode, the DMA controller does a two-cycle transfer (a load followed by a store) as opposed to
the ISA “fly-by” cycle for the SLC88B17. The memory portion of the cycle generates a PCI memory read or memory
write bus cycle, its address representing the selected memory.
The I/O portion of the DMA cycle generates a PCI I/O cycle to one of the four I/O addresses (Table 1).
Note that these cycles must be qualified by an active nISAGNT signal to the SLC88B17.
Table 1 - DMA Cycle vs. I/O Address
DMA CYCLE TYPE
DMA I/O ADDRESS
TC (A2)
PCI CYCLE TYPE
Normal
00h
0
I/O Read/Write
Normal TC
04h
1
I/O Read/Write
Verify
0C0h
0
I/O Read
Verify TC
0C4h
1
I/O Read
For PCI DMA cycles, the I/O address indicates the type of DMA cycle taking place (whether it’s a normal or a verify
cycle, and if this is the last transfer of the buffer). Note that the A2 address line is encoded as the terminal count
signal for PCI cycles; A2 asserted during a PCI I/O cycle indicates the last transfer in the current DMA buffer. To
ensure that non Mobile PC/PCI compliant PCI I/O devices do not confuse Mobile PC/PCI DMA cycles for normal I/O
cycles, the addresses used by PCI DMA cycles correspond to the slave addresses of the Mobile PC/PCI DMA
controller.
All PCI DMA I/O ports are DWord aligned and can be either byte or word in size. This means that any PCI DMA I/O
port are always connected to the lower data lines of the PCI data bus (Table 2). The byte enables also reflect this
during the I/O portion of a PCI DMA cycle. Table 3 illustrates the byte enable for any given PCI DMA cycle.
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