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参数资料
| 型号： | SLC88B17QFP |
| 厂商： | STANDARD MICROSYSTEMS CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | ISA BUS CONTROLLER, PQFP160 |
| 封装： | QFP-160 |
| 文件页数： | 32/54页 |
| 文件大小： | 333K |
| 代理商： | SLC88B17QFP |
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SMSC DS – SLC88B17
Page 38
Rev. 09/28/99
Table 7 - ISA Bus Timing
FUNCTIONAL OPERATING RANGE (VCC=5.0V
±±±± 0.25V, TCASE=0°°°°C TO +85°°°°C)
SYMBOL
PARAMETER
MIN
MAX
UNITS
TYPE
SIZE
NOTES
FIGURE
T144
AEN Hold from nMEMR
Inactive
11
ns
Figure 15
Figure 16
SA[15:0]
T145
SA[15:0] Valid Setup to
nMEMR Active
72
ns
Figure 15
Figure 16
T146
SA[15:0] Valid Hold from
nMEMR Inactive
35
ns
T147
SA[15:0] Valid Float from
nMEMR Inactive
46
120
ns
7
NMEMR, NSMEMR
T148
nMEMR Active Pulse Width
225
ns
Figure 15
Figure 16
T149
nMEMR Tri-State from
nMEMR Inactive
36
120
ns
Figure 16
T150
nMEMR Driven Inactive from
IOCHRDY Active
120
ns
T151
nSMEMR Propagation Delay
from nMEMR
25
ns
Figure 16
IOCHRDY
T152
IOCHRDY Inactive from
nMEMR Active
76
ns
Figure 15
Figure 16
T153
IOCHRDY Valid from nMEMR
Active
76
ns
Figure 16
T154
IOCHRDY Inactive Pulse
Width
120
ns
Figure 16
SLC88B17 DRIVING BUS FROM NREFRESH
T155
SLC88B17 Drives Control &
Address from nREFRESH
Active
5ns
7
Figure 16
Notes:
1.
No-wait-state (nZEROWS) asserted.
2.
This applies to the byte lane that the data has been swapped to.
3.
Data is tri-stated from the standard memory commands (nSMEMR or nSMEMW), when they are generated.
4.
This specification includes both the time the SLC88B17 drives IOCHRDY active and the time it takes the
SLC88B17 to float IOCHRDY.
5.
This applies to the last cycle of a demand mode DMA transfer.
6.
36 ns have been added to the ISA spec to meet nZEROWS setup requirements.
7.
This applies to ISA Master initiated refresh only.
8.
56 ns have been added to the ISA spec to meet nMEMCS16 setup requirements. ISA devices are not supposed
to use the SA address as part of their nMEMCS16 decode. However, some devices do use SA as part of
nMEMCS16 decode.
9.
For back-to-back “sub cycles” generated as a result of byte assembly or disassembly, the spec is 34 ns.
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