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参数资料
| 型号： | SLC88B17QFP |
| 厂商： | STANDARD MICROSYSTEMS CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | ISA BUS CONTROLLER, PQFP160 |
| 封装： | QFP-160 |
| 文件页数： | 9/54页 |
| 文件大小： | 333K |
| 代理商： | SLC88B17QFP |
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SMSC DS – SLC88B17
Page 17
Rev. 09/28/99
IORT
ISA I/O Recovery Timer Register
Offset Address:
40h
Default Value:
4Dh
Access:
Read/Write
This register is used to add additional recovery delay between PCI initiated 16bit and 8bit I/O cycles to the ISA Bus.
SLC88B17 automatically forces a minimum delay of 3.5 SYSCLKs between back to back 16bit and 8bit I/O cycles to
the ISA Bus. The delay is measured from the rising edge of the IO command to the falling edge to the next IO
command. No additional delay is inserted for back to back I/O “sub cycles” generated as a result of byte assembly or
disassembly.
BIT
FUNCTION
7
SYSCLK Divider Select. 1= Reserved. 0 = Divide PCI clock by 4. Sets how the SYSCLK
is generated form the PCI clock.
6
8 bit IO Recovery Enable. When set to a 1, enables the recovery time programmed in
bits
[5-3].
When set to a 0, disables programmed recovery times and uses the default timing of 3.5
SYSCLKs for 8-bit I/O recovery times.
5-3
8 bit IO recovery times when bit 6 is set to 1. Programmable delays between back to
back
8 bit PCI cycles to an ISA I/O slave is shown in terms of additional ISA clock
recovery cycles (SYSCLK).
001: 1
010: 2
011: 3
100: 4
101: 4
110: 6
111: 7
000:8
2
16 bit IO Recovery Enable. When set to a 1, enables the recovery time programmed in
bits[1-0].
When set to a 0, disables programmed recovery times and uses the default timing of 3.5
SYSCLKs.
1-0
16 bit IO recovery times (actual recovery clock counts) when bit 2 is set to 1.
01: 1
10: 2
11: 3
00: 4
MISCON
Miscellaneous Control Register
Offset Address:
041h
Default Value:
00h
Access:
Read/Write
BIT
FUNCTION
7
Passive Release Enable.
0: Disable Passive Release.
1: Enable.
6-2
Reserved.
1
AT DRAM Slow Refresh.
0: Disable.
1: Enable. Refresh interval is extended to 208 us.
0
AT Refresh Option.
0: Disable
1: Enable.
MISA_STS
MISA Error Status Register
Offset Address:
42h
Default Value:
00h
Access:
Read Only
This register reflects the error status of the ISA interface.
BIT
FUNCTION
7-3
Reserved.
2
nIOCHK Pin State. This bit reflects the inverse state of nIOCHK pin on the ISA Bus.
When this bit is set, SLC88B17 pulses nSERR (if enabled via the PCICMD register).
1
Reserved.
0
Byte Lane Error (BYTERR). This bit is set if SLC88B17 detects an illegal byte lane
combination for a PCI I/O cycles. When this condition is detected, SLC88B17 signals a
target abort and pulses the nSERR signal (if enabled via the PCICMD register).
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