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参数资料
| 型号： | SLC88B17QFP |
| 厂商： | STANDARD MICROSYSTEMS CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | ISA BUS CONTROLLER, PQFP160 |
| 封装： | QFP-160 |
| 文件页数： | 54/54页 |
| 文件大小： | 333K |
| 代理商： | SLC88B17QFP |
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SMSC DS – SLC88B17
Page 9
Rev. 09/28/99
NAME
TYPE
DESCRIPTION
nIRDY
I/O
Initiator Ready. The signal is asserted when the SLC88B17 is ready for a data
transfer. A data phase is completed on any clock both nIRDY and nTRDY are
sampled asserted.
nIRDY is an input to the SLC88B17 when the SLC88B17 is the target and an output
when the SLC88B17 is an initiator. It remains tri-stated until driven by the SLC88B17
as a master.
During Reset: High-Z
After Reset: High-Z
nTRDY
I/O
Target Ready. The signal is asserted when the SLC88B17 is ready for a data
transfer. A data phase is completed on any clock both nIRDY and nTRDY are
sampled asserted.
nTRDY is an input to the SLC88B17 when the SLC88B17 is the initiator and an
output when the SLC88B17 is a target. It remains tri-stated until driven by the
SLC88B17 as a target.
During Reset: High-Z
After Reset: High-Z
nSTOP
I/O
Stop. nSTOP indicates that the SLC88B17, as a Target, is requesting the initiator to
stop the current transaction. As an initiator, nSTOP causes the SLC88B17 to stop the
current transaction.
nSTOP is an output when the SLC88B17 is a Target and an input when the
SLC88B17 is an initiator. nSTOP is tri-stated from the leading edge of nPCIRST, and
it remains tri-stated until driven by the SLC88B17 as a slave.
During Reset: High-Z
After Reset: High-Z
IDSEL
I
Initialization Device Select. IDSEL is used as a chip select during PCI configuration
read and write cycles. The SLC88B17 samples IDSEL during the address phase of a
transaction. The SLC88B17 responds by asserting nDEVSEL if IDSEL is sampled
active during configuration cycle.
nSERR
OD
System Error. nSERR can be driven active by any PCI device that detects a system
error condition.
During Reset: High-Z
After Reset: High-Z
PAR
O
Parity. PAR is “even” parity and is calculated on 36 bits (AD[31-0] and nC/BE[3-0]).
PAR is calculated on 36 bits regardless of the valid byte enables. PAR is driven and
tri-stated identically to the AD[31-0] lines except that PAR is delayed by exactly one
PCI clock.
PAR is an output during the address phase for all SLC88B17 initiated transactions. It
is also an output during the data phase when the SLC88B17 is the initiator of a PCI
write transaction, and when it is the target of a read transaction.
During Reset: High-Z
After Reset: High-Z
nPCIRST
I
Reset. This is a PCI reset input signal. In response to the assertion of nPCIRST, the
SLC88B17 will assert ISA RSTDRV to reset ISA devices.
ISA Interface Signals
NAME
TYPE
DESCRIPTION
SA[19-0]
I/O
System Address. The address lines SA[19-17] that are coincident with LA[19-17]
are defined to have the same values as LA[19-17] for all memory cycles. For I/O
accesses, only SA[15-0] are used, and SA[19-16] are undefined. SA[19-0] are
outputs when the SLC88B17 owns the ISA bus. They are inputs when an external
ISA master owns the ISA bus.
During Reset: High-Z
After Reset: Undefined
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