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| 型号： | SN74V3650-6PEU |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| 中文描述： | 的3.3V的CMOS先入先出存储器 |
| 文件页数： | 45/50页 |
| 文件大小： | 729K |
| 代理商： | SN74V3650-6PEU |
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SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024
×
36, 2048
×
36, 4096
×
36, 8192
×
36, 16384
×
36, 32768
×
36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A
–
NOVEMBER 2001
–
REVISED MARCH 2003
45
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
depth-expansion configuration (FWFT mode only)
The SN74V3640 easily can be adapted to applications requiring depths greater than 1024 for the SN74V3640,
2048 for the SN74V3650, 4096 for the SN74V3660, 8192 for the SN74V3670, 16384 for the SN74V3680, and
32768 for the SN74V3690, with an 18-bit bus width. In FWFT mode, the FIFOs can be connected in series (the
data outputs of one FIFO connected to the data inputs of the next), with no external logic necessary. The
resulting configuration provides a total depth equivalent to the sum of the depths associated with each single
FIFO. Figure 24 shows a depth expansion using two SN74V3640, SN74V3650, SN74V3660, SN74V3670,
SN74V3680, and SN74V3690 devices.
Care should be taken to select FWFT mode during master reset for all FIFOs in the depth-expansion
configuration. The first word written to an empty configuration passes from one FIFO to the next (ripple down)
until it finally appears at the outputs of the last FIFO in the chain. No read operation is necessary, but the RCLK
of each FIFO must be free running. Each time the data word appears at the outputs of one FIFO, that device
’
s
OR line goes low, enabling a write to the next FIFO in line.
REN
Data In
Write Enable
Write Clock
SN74V3640
SN74V3650
SN74V3660
SN74V3670
SN74V3680
SN74V3690
FWFT/SI
Transfer Clock
WCLK
WEN
IR
Dn
RCLK
OR
REN
OE
Qn
WCLK
WEN
IR
Dn
RCLK
OR
OE
Qn
Read Clock
Read Enable
Input Ready
Output Ready
Output Enable
Data Out
GND
n
n
n
SN74V3640
SN74V3650
SN74V3660
SN74V3670
SN74V3680
SN74V3690
FWFT/SI
FWFT/SI
Figure 21. 2048
×
36, 4096
×
36, 8192
×
36, 16384
×
36, 32768
×
36, 65536
×
36
Depth-Expansion Block Diagram
For an empty-expansion configuration, the amount of time it takes for OR of the last FIFO in the chain to go low
(i.e., valid data to appear on the last FIFO
’
s outputs) after a word has been written to the first FIFO is the sum
of the delays for each FIFO:
(n
–
1)
(4
transfer clock)
3t
RCLK
Where:
n
t
RCLK
= RCLK period
= number of FIFOs in the expansion
Note that extra cycles should be added for the possibility that the t
sk1
specification is not met between WCLK
and the transfer clock, or RCLK and the transfer clock, for the OR flag.
The ripple-down delay is noticeable only for the first word written to an empty-depth-expansion configuration.
There will be no delay evident for subsequent words written to the configuration.
The first free location created by reading from a full-depth-expansion configuration will bubble up from the last
FIFO to the previous one until, finally, it moves into the first FIFO of the chain. Each time a free location is created
in one FIFO of the chain, that FIFO
’
s IR line goes low, enabling the preceding FIFO to write a word to fill it.
P
(1)
相关PDF资料 |
PDF描述 |
|---|---|
| SN74V3660-10PEU | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V3660-15PEU | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V3670-10PEU | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V3670-15PEU | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| SN74V3690-15PEU | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SN74V3650-7PEU | 功能描述:先进先出 2048 x 36 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V3660-10PEU | 功能描述:先进先出 4096 x 36 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V3660-15PEU | 功能描述:先进先出 4096 x 36 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V3660-6PEU | 功能描述:先进先出 4096 x 36 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V3660-7PEU | 功能描述:先进先出 4096 x 36 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
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