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参数资料
| 型号： | ST7285C |
| 厂商： | 意法半导体 |
| 英文描述： | 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES |
| 中文描述： | 8位微控制器48,000铁路发展策略光盘，3K内存，ADC，两个定时器，2个SPI，I2C和脊髓损伤接口 |
| 文件页数： | 54/117页 |
| 文件大小： | 748K |
| 代理商： | ST7285C |
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ST7285C
4.5 I
2
C BUS INTERFACE
4.5.1 Introduction
The I
2
C Bus Interface serves as an interface be-
tween the MCU and the serial I
2
C bus. It provides
both multimaster and multislave functions, and
controls all I
2
C bus-specific sequencing, protocol,
arbitration and timing.
4.5.2 General Features
– Parallel bus/I
2
C protocol converter
– Multi-Master capability
– Interrupt generation
– Standard I
2
C mode/Fast I
2
C mode
– 7-bit Addressing/10-bit Addressing
4.5.2.1 I
2
C Master Mode Features:
– Flag indicating when the I
2
C bus is in use
– Flag indicating the loss of arbitration
– Flag indicating the end of the byte transmission
– Transmitter/Receiver flag
– Clock generation
4.5.2.2 I
2
C Slave Mode Features:
– Start bit detection flag
– Detection of a misplaced Start or Stop condition
– Detection of a problem during transfer
– Address Matched detection
– General call detection
– Flag indicating the end of the byte transmission
– Transmitter/Receiver flag
4.5.3 Functional Description
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
handshake. The interrupts are enabled or disabled
by software. The interface is connected to the I
2
C
bus by a data pin (SDA) and by a clock pin (SCL).
It can be connected both with a standard I
2
C bus
and a Fast I
2
C bus. This selection is made by soft-
ware.
The interface can operate in the four following
modes:
– Master transmitter
– Master receiver
– Slave transmitter
– Slave receiver
When it is inactive, it operates in Slave Mode.
This interface enables the multimaster function
thanks to an automatic switch between Master and
Slave mode in the event of a loss of arbitration:the
Slave process is always active when a start condi-
tion is detected on the SDA line. When acting as
Master, it initiates a data transfer and generates
the clock signal. A serial data transfer always be-
gins with a start condition and ends with a stop
condition. Both start and stop conditions are soft-
ware generated in Master mode. In Slave mode,
the interface is capable of recognising its own ad-
dress (7-bit or 10-bit), a general call address or a
start byte. The general call may be enabled or dis-
abled by software.
Data and addresses are transferred as 8-bit bytes,
MSB first. The first byte following the start condi-
tion in 7-bit addressing (two first bytes in 10-bit ad-
dressing) is the address byte; it is always transmit-
ted in Master mode. A 9th clock pulse follows the 8
clock cycles of a byte transfer, during which the re-
ceiver must send an acknowledge bit to the trans-
mitter. Acknowledge may be enabled and disabled
by software.
When in Transmitter mode, the interface waits for
the MCU to write the byte in the Data Register, by
holding the clock line low before transmission;
when in Receiver mode, it waits for the MCU to
read the byte in the Data Register by holding the
clock line low after reception.
The I
2
C Bus Interface has seven internal registers.
Three of these are used for interface initialization
(Own Address Registers and Clock Control Regis-
ter). The remaining four registers are used during
data transmission/reception (Data Register, Con-
trol Register and Status Register).
The SCL frequency (F
scl
) is controlled by a pro-
grammable clock divider which depends on the
I
2
C bus mode. The I
2
C interface address is stored
in two registers (OAR) in order to allow 10-bit ad-
dressing.
The Peripheral Enable bit (bit 6) of the I
2
C Control
Register activates the I
2
C interface and configures
the I/O as I
2
C pins. The speed of the I
2
C interface
may be selected between 100KHz and 400KHz.
When the I
2
C cell is enabled, PA4 and PA6 are
configured as open-drain. In this case, the external
pull-up resistance should be 10K
or more.
When the I
2
C cell is disabled, PA4 and PA6 revert
to being standard I/O port pins.
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