- 您现在的位置：买卖IC网 > PDF目录385871 > ST7285C (意法半导体) 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES PDF资料下载
参数资料
| 型号： | ST7285C |
| 厂商： | 意法半导体 |
| 英文描述： | 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES |
| 中文描述： | 8位微控制器48,000铁路发展策略光盘，3K内存，ADC，两个定时器，2个SPI，I2C和脊髓损伤接口 |
| 文件页数： | 60/117页 |
| 文件大小： | 748K |
| 代理商： | ST7285C |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页当前第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页
60/117
ST7285C
I
2
C BUS INTERFACE
(Cont’d)
STATUS REGISTER 1 (SR1)
Address: 0029h
Reset Value: 00h
—
Read Only
b7:
SR2F
Status Register 2 Flag
SR2F is set when at least one flag in the Status
Register 2 is set. It is cleared when all these flags
are reset.
b6:
ADD10
10 bit Master Addressing Mode
ADD10 is set when the 10 bit addressing mode
header (”11110xxx”) is sent as the first address
byte. When this bit is set, an interrupt is sent to the
microcontroller if ITE is set
This bit is cleared by a read of the Status Register,
followed by a write in the Data Register. It is also
cleared when the peripheral is disabled (PE=0) or
by reset.
b5:
TRA
Transmitter/Receiver
TRA is set when the interface is in data transmis-
sion mode.
It is cleared by the detection of a stop condition, by
a loss of the bus arbitration (ARLO set). It is also
cleared when the peripheral is disabled (PE=0) or
by reset.
b4:
BUSY
Bus Busy
BUSY bit is active when there is a communication
in progress on line.
The detection of the communications is always ac-
tive (even if the peripheral s disabled).
This bit is set by the detection of a Start condition
and it is cleared by the detection of a Stop condi-
tion or by reset.
b3:
BTF
Byte Transfer Finished
- In transmitter mode, BTF bit is set after the trans-
mission of a data byte and an acknowledge clock
pulse.
It is cleared by a read of the Status Register (with
BTF set), followed by a write in the Data Register.
In receiver mode, BTF bit is set after the reception
of the acknowledge of a byte.
It is cleared by a reading of the Status Register
(with BTF set), followed by a read of the Data Reg-
ister.
It is also cleared when the peripheral is disabled
(PE=0) or by reset.
When BTF is set, the I
2
C interrupt occurs if ITE is
set. Then the microcontroller must access the data
register.
b2:
ADSL
Addressed as Slave
ADSL bit is set when the address comparator rec-
ognizes either its own Slave address or the gener-
al call address. When this bit is set , an interrupt is
sent to the microcontroller if ITE is set.
This bit is cleared by a read of the status register
(when ADSL is set). Itis also cleared when the pe-
ripheral is disabled (PE=0) or by reset.
b1:
M/SL
Master/Slave
M/SL bit is set when the interface generates a
Start condition. When it is set, the interface oper-
ates in Master mode.
It is cleared by the detection of a Stop condition,
by a loss of arbitration, by reset or when the pe-
ripheral is disabled (PE=0).
b0:
SB
Start Bit ( in Master mode)
In Master mode , SB bit is set when the hardware
has generated a Start condition. When this bit is
set, an interrupt is sent to the microcontroller if ITE
is set. Then the microcontroller must write the ad-
dress byte in the data register.
This bit is cleared by a read of the status register
(when SB is set), followed by a write in the data
register. It is also cleared when the peripheral is
disabled (PE=0) or by reset.
7
0
SR2F
ADD10
TRA
BUSY
BTF
ADSL
M/SL
SB
相关PDF资料 |
PDF描述 |
|---|---|
| ST72T85A5Q6 | 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES |
| ST730C08L3 | PHASE CONTROL THYRISTORS |
| ST730C08L3L | PHASE CONTROL THYRISTORS |
| ST730C12L0 | PHASE CONTROL THYRISTORS |
| ST730C12L0L | PHASE CONTROL THYRISTORS |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST7-28B56 | 功能描述:电源变压器 SPLIT BOBBIN HORZ MOUNT XFMR RoHS:否 制造商:Triad Magnetics 功率额定值:12 VA 初级电压额定值:115 V / 230 V 次级电压额定值:12 V / 24 V 安装风格:SMD/SMT 一次绕组:Dual Primary Winding 二次绕组:Dual Secondary Winding 长度:2.5 in 宽度:2 in 高度:1.062 in |
| ST72A | 制造商:DGS 功能描述: |
| ST72C104G1B6 | 功能描述:8位微控制器 -MCU Flash 4K SPI RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ST72C104G1M1 | 制造商:STMicroelectronics 功能描述:8-BIT MICROCONTROLLER - Bulk |
| ST72C104G1M6 | 功能描述:8位微控制器 -MCU Flash 4K SPI RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
发布紧急采购，3分钟左右您将得到回复。