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参数资料
型号： ST7285C
厂商： 意法半导体
英文描述： 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES
中文描述： 8位微控制器48,000铁路发展策略光盘，3K内存，ADC，两个定时器，2个SPI，I2C和脊髓损伤接口
文件页数： 77/117页
文件大小： 748K
代理商： ST7285C
77/117
ST7285C
RDS G.B.S.
(Cont’d)
QR0 - Quality Register
b7-6 =
QR[1:0]
Receives QUALITY sequence.
b5-0 = reserved; always read as “0”.
QRx - Quality Registers
QR1.
b7-0 contain bits 9-2 of a received QUALITY
sequence.
QR2.
b7-0 contain bits 17-10 of a received QUAL-
ITY sequence.
QR3.
b7-0 contain bits 25-18 of a received QUAL-
ITY sequence.
4.9.4
Acquisition
of
Synchronization
New group and block synchronization is neces-
sary after switching on the receiver, on tuning to a
new station, or after a prolonged signal fade. The
syndrome is calculated for every single received
RDS-data bit. All valid syndromes corresponding
to offset words A to E are shown inTable 9.
Blocks within each group are identified by offset
words A, B, C or C’, and D. This fact is used for
block and group synchronization. Detection and
coding of block E is enabled by control bit US in
Polynomial Register 0. Block E is used for addi-
tional Radio Paging Information in North America.
For detailed information, see United States RDBS
Standard Specification, published by NRSC.
Group
and
Block
4.9.5 Application Tips
It is recommended not to load CNA with “0”, be-
cause this would generate a CNAzero-count inter-
rupt after every syndrome calculation, initiated ei-
ther by positive edge of RDSCLK or by writing a
“1” to CAL.
All data and flags are derived from the positive
edge of RDSCLK and thus are only valid for one
period of this clock.
All interrupt service routines (VSI or CNI inter-
rupts) must be completed before the next positive
edge of RDSCLK (i.e. within 842ms), except when
Error Correction Mode is selected (ECM=1). In this
case, the interrupt service may take up to 21.9ms
in BLOCK_SYNC mode.
4.9.6 Block Synchronization Software
There are many strategies to achieve RDS Block
Synchronization, A standard method with a simpli-
fied synchronization criteria is briefly described.
The software starts in BIT-SYNC mode. CNA is
loaded with “1” and the counter interrupt is ena-
bled on CNA zero-count. On each interrupt, the
syndrome is checked via the VSI flag until VSI is
“1”. Then the blockcode BL[2:0] and the CNA
count are saved; the software continues until the
next Valid Syndrome detection.
If bit distance (26) and block order are correct, the
RDS Block Synchronization is achieved, and the
software can switch to BLOCK_SYNC mode. The
software can easily maintain Block Synchroniza-
tion by checking the VSI and ORD flags, the latter
indicates correct block order.
This method does not respect dummy syndromes
(valid syndromes appearing between two valid
blocks).
An optional GRP_SYNC mode may be entered for
RDS standby operation, using the appropriate
counter interrupt selection.
4.9.7 Error Correction software
Software triggered syndrome calculation, a sec-
ond 26-bit shift register and a 26-bit quality regis-
ter, allow highly flexible error correction by soft-
ware, using the quality signal information from the
RDS demodulator.
A quality “low” state indicates an uncertain corre-
sponding RDSDAT bit. Because of the differential
decoding of RDSDAT, not only the RDSDAT bit
pointed to by Quality, but also the following RDS-
DAT bit may be wrong. Thus a single quality error
can represent a single or a double data bit error. A
single quality error within one block is indicated by
the SQE flag, multiple quality errors within one
block are indicated by the MQE flag.
The software starts error correction by setting
ECM to “1”, to make the main shift registers SR3-
SR0 available for software triggered syndrome
calculations, which may take longer than one peri-
od of RDSCLK (842ms).
New incoming RDSDAT-bits are stored in the par-
allel shift registers DR3-DR0. Moreover, the cur-
rent contents of the quality registers QR3-QR0,
must be saved in RAM, in order to be used for the
following error correction.
Error correction may be performed by reversing
the RDSDAT bits in shift registers SR3-SR0,
which are indicated as bad in the quality register
(with respect to RDSDAT differential decoding).
After each reverse, a new syndrome calculation is
started (CAL=1) and checked (VSI). Single quality
errors, representing a 1 or 2 bit RDSDAT error
may be corrected with high security.
On completion of the correction, the contents of
DR3-DR0 must be copied back into shift registers
SR3-SR0, and ECM must be set to “0”.
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