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| 型号： | ST7285C |
| 厂商： | 意法半导体 |
| 英文描述： | 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES |
| 中文描述： | 8位微控制器48,000铁路发展策略光盘，3K内存，ADC，两个定时器，2个SPI，I2C和脊髓损伤接口 |
| 文件页数： | 62/117页 |
| 文件大小： | 748K |
| 代理商： | ST7285C |
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ST7285C
I
2
C BUS INTERFACE
(Cont’d)
4.5.6.3 Slave Sending
The Slave waits for the microcontroller to write in
the Data Register. Then it receives data in the
Shift Register and sends it on the SDA line. When
the acknowledge bit is received, the BTF flagis set
and an interrupt is generated if ITE is set.
- Detection of a Stop or Start condition during a
byte transfer: the state machine is reset, the BERR
flag is set and an interrupt is generated.
- Detection of a Start condition after an acknowl-
edge time-slot: the state machine is reset and it
starts a new process. So, the flag ADSL is set and
an interrupt is generated if ITE is set.
- Detection of a Stop condition after an acknowl-
edge time-slot: the state machine is reset. Then
the flag SSTOP is set and an interrupt is generat-
ed if ITE is set.
4.5.6.4 Master mode
The interface operates in Master mode after gen-
erating a Start condition. So, the Start flag must be
set in the control register and the I
2
C bus must be
free (Busy bit at logic low level).
Once the Start condition is generated, the M/SL
and SB flags are set and an interrupt is generated
if ITE is set. The interface waits for the microcon-
troller to write the Slave address in the Data Reg-
ister by holding the SCL line low.
The address byte is then sent on the SDA line, an
acknowledge clock pulse is sent on the SCL line
and an interrupt is generated if ITE is set. The in-
terface waits for the MCU to write to the Control
Register by holding the SCL line low. If there is no
acknowledge, the AF flag is set and the Master
must write a Start or a Stop in the ControlRegister.
The state machine then enters a send or a receive
process, depending on the stateof the Data Direc-
tion bit (least significant bit); an interrupt is gener-
ated if ITE is set.
If the Master loses control of bus arbitration, there
will be no acknowledge. The AF flag is set and the
Master must write a Start or a Stop in the control
register; the ARLO flag is set, the M/SL flag is
cleared and the process is reset. An interrupt is
generated if ITE is set.
4.5.6.5 Master Sending
The Master waits for the MCU to write in the Data
Register by holding the SCL line low. Then the
byte is received in the shift register and is sent on
the SDA line. The BTF flag is set and an interrupt
is generated if ITE is set.
- Detection of a Stop or of a Start condition during
a byte transfer: the BERR flag is set and an inter-
rupt is generated if ITE is set.
- The Stop bit is set in the Control Register: a Stop
condition is generated after the transfer of the cur-
rent byte, the M/SL flag is cleared and the state
machine is reset. Then an interrupt is generated if
ITE is set.
- The Start bit is set in the Control Register: the
state machine is reset and it starts a new process.
The SB flag is set and an interrupt is generated if
ITE is set.
- There is no acknowledge: the AF flag is set and
an interrupt is generated if ITE is set.
4.5.6.6 Master Receiving
The Master receives a byte from the SDA line into
the shift register and it sends it to the Data Regis-
ter. So, it generates an acknowledge bit if the ACK
bit is set and it generates an interrupt if ITE is set.
Then it waits for the microcontroller to read the
Data Register by holding SCL line low.
- A detection of a Stop or a Start condition during a
byte reception: the flag BERR is set and an inter-
rupt is generated if ITE is set.
- The Stop bit is set in the Control Register: a Stop
condition is generated after the transfer of the cur-
rent byte, the M/SL flag is cleared and the state
machine is reset. Then an interrupt is generated if
ITE is set.
- The Start bit is set in the Control Register: the
state machine is reset and starts a new process.
So, the flag SB is set and an interrupt is generated
if ITE is set.
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