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参数资料
型号： ST92E141K4D1
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 16-BIT, UVPROM, 25 MHz, MICROCONTROLLER, CDIP32
封装： WINDOWED, SHRINK, CERAMIC, DIP-32
文件页数： 119/178页
文件大小： 1097K
代理商： ST92E141K4D1
45/178
ST92141 - INTERRUPTS
ARBITRATION MODES (Cont’d)
End of Interrupt Routine
The iret Interrupt Return instruction executes
the following steps:
– The Flag register is popped from system stack.
– If ENCSR is set, CSR is popped from system
stack.
– The PC high byte is popped from system stack.
– The PC low byte is popped from system stack.
– All unmasked Interrupts are enabled by setting
the CICR.IEN bit.
– The priority level of the interrupted routine is
popped from the special register (NICR) and
copied into CPL.
– If ENCSR is reset, CSR is used instead of ISR,
unless the program returns to another nested
routine.
The suspended routine thus resumes at the inter-
rupted instruction.
Figure 19 contains a simple example, showing that
if the ei instruction is not used in the interrupt
service routines, nested and concurrent modes
are equivalent.
Figure 20 contains a more complex example
showing how nested mode allows nested interrupt
processing (enabled inside the interrupt service
routines using the ei instruction) according to
their priority level.
Figure 20. Complex Example of a Sequence of Interrupt Requests with:
- Nested mode
- IEN set to 1 during the interrupt routine execution
INT 2
INT 3
CPL=3
INT 0
CPL=0
INT6
6
5
4
3
2
1
0
7
MAIN
INT 5
INT 4
INT0
INT4
INT3
INT2
CPL is set to 7
CPL=5
CPL=4
CPL=2
CPL=7
ei
INTERRUPT 2 HAS PRIORI TY LEVEL 2
INTERRUPT 3 HAS PRIORI TY LEVEL 3
INTERRUPT 4 HAS PRIORI TY LEVEL 4
INTERRUPT 5 HAS PRIORI TY LEVEL 5
INT 2
INT 4
CPL=2
CPL=4
INT 5
CPL=5
MAIN
ei
INT 2
CPL=2
INT 6
CPL=6
INT5
INT2
ei
INTERRUPT 6 HAS PRIORI TY LEVEL 6
INTERRUPT 0 HAS PRIORI TY LEVEL 0
CPL6 > CPL3:
INT6 pending
CPL2 < CPL4:
Serviced just after ei
Priority Level of
Interrupt Request
ei
1
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