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参数资料
型号： ST92E141K4D1
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 16-BIT, UVPROM, 25 MHz, MICROCONTROLLER, CDIP32
封装： WINDOWED, SHRINK, CERAMIC, DIP-32
文件页数： 43/178页
文件大小： 1097K
代理商： ST92E141K4D1
137/178
ST92141 - SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
7.5.4 Functional Description
Figure 72 shows the serial peripheral interface
(SPI) block diagram.
This interface contains 4 dedicated registers:
– A Control Register (CR)
– A Prescaler Register (PR)
– A Status Register (SR)
– A Data Register (DR)
Refer to the CR, PR, SR and DR registers in Sec-
tion 7.5.6for the bit definitions.
7.5.4.1 Master Configuration
In a master configuration, the serial clock is gener-
ated on the SCK pin.
Procedure
– Define the serial clock baud rate by setting/re-
setting the DIV2 bit of PR register, by writing a
prescaler value in the PR register and pro-
gramming the SPR0 & SPR1 bits in the CR
register.
– Select the CPOL and CPHA bits to define one
of the four relationships between the data
transfer and the serial clock (see Figure 74).
– The SS pin must be connected to a high level
signal during the complete byte transmit se-
quence.
– The MSTR and SPOE bits must be set (they
remain set only if the SS pin is connected to a
high level signal).
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
Transmit sequence
The transmit sequence begins when a byte is writ-
ten the DR register.
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if the SPIS and SPIE
bits are set.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SR register while the SPIF bit
is set
2. A write or a read of the DR register.
Note: While the SPIF bit is set, all writes to the DR
register are inhibited until the SR register is read.
9
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