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参数资料
型号： ST92E141K4D1
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 16-BIT, UVPROM, 25 MHz, MICROCONTROLLER, CDIP32
封装： WINDOWED, SHRINK, CERAMIC, DIP-32
文件页数： 29/178页
文件大小： 1097K
代理商： ST92E141K4D1
124/178
ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont’d)
7.4.7 NMI management
Figure 70 shows how the external input NMI signal
is managed by the IMC peripheral.
After an ST9 reset, the NMIE bit in the PCR1 reg-
ister is cleared, which means that NMI signal com-
ing from the external pin is sent, as is, to the ST9
core without affecting the IMC peripheral.
If the NMIE bit is set, when an NMI event occurs
on the external pin, it will be acknowledged (de-
pending on the value of the NMIL bit in the PSR
register). In this case:
– The NMI bit in the IMCIVR register is set
– The dedicated output pins of the IMC are put in
high impedance
– A high level signal is sent to the ST9 Top Level
interrupt
– The OPE bit is cleared (as the NMI interrupt sig-
nal is no longer active)
Notes:
1. Because the signal to the ST9 top level interrupt
is active high, the TLTEV bit in the EIVR register
must be set.
2. When the user wants to leave the NMI interrupt
routine, it is strongly recommended to verify, be-
fore leaving the routine, that the NMI pending bit
(bit 3 of IMCIVR) is really at “0”. To do this, the
user can try to write the NMI pending bit to “0” re-
peatedly until it has successfully been cleared.
The NMI pending bit in IMCIVR register can be
written to “0” only if the external NMI signal is no
longer active. This makes sure that no NMI event
will be lost. If the user leaves the NMI interrupt rou-
tine without clearing the NMI pending bit, no other
NMI interrupt can be issued afterwards because
the ST9 top level interrupt is edge sensitive.
Figure 70. NMI management by the IMC peripheral
0
1
NMIE
bit
NMI
bit
Level
selection
NMIL
bit
NMI to ST9 core
NMI from EXT pin
9
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