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参数资料
型号： ST92E141K4D1
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 16-BIT, UVPROM, 25 MHz, MICROCONTROLLER, CDIP32
封装： WINDOWED, SHRINK, CERAMIC, DIP-32
文件页数： 3/178页
文件大小： 1097K
代理商： ST92E141K4D1
100/178
ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
7.3.3.3 Input Capture
In this section, the index,
i, may be 1 or 2.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition detected by the
ICAP
i pin (see figure 5).
IC
i Rregister is a read-only register.
The active transition is software programmable
through the IEDG
i bit of the Control Register (CRi).
Timing resolution is one count of the free running
counter: (INTCLK/CC[1:0]).
Procedure
To use the input capture function select the follow-
ing in the CR2 register:
– Select the timer clock (CC[1:0] (see Table 22
Clock Control Bits).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit.
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit.
When an input capture occurs:
– ICF
i bit is set.
– The IC
iR register contains the value of the free
running counter on the active transition on the
ICAP
i pin (see Figure 57).
– A timer interrupt is generated if the ICIE bit is set
and the ICIS bit (or EFTIS bit if only global inter-
rupt is available) is set. Otherwise, the interrupt
remains pending until both conditions become
true.
Clearing the Input Capture interrupt request is
done by:
1. Reading the SR register while the ICF
i bit is set.
2. An access (read or write) to the IC
iLR register.
Note: After reading the IC
iHR register, transfer of
input capture data is inhibited until the IC
iLR regis-
ter is also read.
The IC
iR register always contains the free running
counter value which corresponds to the most re-
cent input capture.
MS Byte
LS Byte
IC
iRICiHR
IC
iLR
9
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