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参数资料
型号： ST92E141K4D1
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 16-BIT, UVPROM, 25 MHz, MICROCONTROLLER, CDIP32
封装： WINDOWED, SHRINK, CERAMIC, DIP-32
文件页数： 7/178页
文件大小： 1097K
代理商： ST92E141K4D1
104/178
ST92141 - EXTENDED FUNCTION TIMER (EFT)
EXTENDED FUNCTION TIMER (Cont’d)
7.3.3.5 Forced Compare Mode
In this section
i may represent 1 or 2.
The following bits of the CR1 register are used:
When the FOLV
i bit is set, the OLVLi bit is copied
to the OCMP
i pin. The OLVLi bit has to be toggled
in order to toggle the OCMP
i pin when it is enabled
(OC
iE bit=1).
The OCF
i bit is not set, and thus no interrupt re-
quest is generated.
7.3.3.6 One Pulse Mode
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure
To use one pulse mode, select the following in the
the CR1 register:
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after the pulse.
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin during the pulse.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit
.
And select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then dedi-
cated to the Output Compare 1 function.
– Set the OPM bit.
– Select the timer clock CC[1:0] (see Table 22
Clock Control Bits).
Load the OC1R register with the value corre-
sponding to the length of the pulse (see the formu-
la in Section 7.3.3.7).
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin. When the value of the counter
is equal to the value of the contents of the OC1R
register, the OLVL1 bit is output on the OCMP1
pin, (See Figure 60).
Note: The OCF1 bit cannot be set by hardware in
one pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
The ICF1 bit is set when an active edge occurs
and can generate an interrupt if the ICIE bit is set.
When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
Figure 60.
One Pulse Mode Timing
FOLV2 FOLV1 OLVL2
OLVL1
event occurs
Counter is
initialized
to FFFCh
OCMP1 = OLVL2
Counter
= OC1R
OCMP1 = OLVL1
When
on ICAP1
One pulse mode cycle
COUNTER
....
FFF C FFF D FFF E
2ED0
2ED1 2ED2
2ED3
FFFC FFFD
OLVL2
OLVL1
ICAP1
OCMP1
compare1
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1
9
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