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参数资料
型号： ST92E141K4D1
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 16-BIT, UVPROM, 25 MHz, MICROCONTROLLER, CDIP32
封装： WINDOWED, SHRINK, CERAMIC, DIP-32
文件页数： 61/178页
文件大小： 1097K
代理商： ST92E141K4D1
153/178
ST92141 - ANALOG TO DIGITAL CONVERTER (ADC)
REGISTER DESCRIPTION (Cont’d)
COMPARE RESULT REGISTER (CRR)
R252 - Read/Write
Register Page: 63
Reset Value: 0000 1111 (0Fh)
The result of the comparison between the current
value of data registers 6 and 7 and the threshold
registers is stored in the 4 most significant bits of
this register.
Bit 7 = C7U:
Compare Reg 7 Upper threshold
Set when converted data is greater than or equal
to the threshold value. Not affected otherwise.
Bit 6 = C6U:
Compare Reg 6 Upper threshold
Set when converted data is greater than or equal
to the threshold value. Not affected otherwise.
Bit 5 = C7L:
Compare Reg 7 Lower threshold
Set when converted data is less than the threshold
value. Not affected otherwise.
Bit 4 = C6L:
Compare Reg 6 Lower threshold
Set when converted data is less than the threshold
value. Not affected otherwise.
These bits should be reset at the end of the “Out of
Range” interrupt service routine.
Note: Any software reset request of the ICR, will
also cause all the compare status bits to forced by
hardware to zero, in order to prevent possible
overwriting if an interrupt request occurs between
reset and the Interrupt request software reset.
Bit 3 = undefined, return ’1’ when red.
Bit 2:0 = PR[2:0]:
Clock divider bits
These bits enable a frequency division factor de-
pending on the value stored:
Table 30. Frequency Division Factors
Warning: If the prescaler programming value is
changed during a conversion, the user has to re-
start the conversion (i.e. simply rewriting the CLR
register with the same value).
70
C7U
C6U
C7L
C6L
X
PR2
PR1
PR0
PR[2:0]
bits
Freq. Div.
Factor
(FDF)
Max. con-
version
time
(INTCLK)
Min. sam-
pling time
(INTCLK)
11 1
11 0
10 1
10 0
01 1
01 0
00 1
00 0
1
4
6
8
10
12
14
16
138
552
828
1104
1380
1656
1932
2208
84
336
504
672
840
1008
1176
1344
9
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