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参数资料
型号： ST92E141K4D1
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 16-BIT, UVPROM, 25 MHz, MICROCONTROLLER, CDIP32
封装： WINDOWED, SHRINK, CERAMIC, DIP-32
文件页数： 31/178页
文件大小： 1097K
代理商： ST92E141K4D1
126/178
ST92141 - 3-PHASE INDUCTION MOTOR CONTROLLER (IMC)
INDUCTION MOTOR CONTROLLER (Cont’d)
INTERRUPT PENDING REGISTER (IPR)
R243 - Read/Write
Register Page: 51
Reset Value: 0000 0000 (00h)
Bit 7 = CM0:
Compare 0 of PWM pending bit.
This bit is set by hardware when the PWM counter
reaches the value in the Compare 0 register while
CM0E=1. The CM0 bit must be cleared by soft-
ware.
0: No CMP0 interrupt occurred
1: CMP0 interrupt pending
Bit 6 = CPT:
Capture of Tacho counter pending bit.
This bit is set by hardware when a Tacho signal
event occurs while CPTE=1. The CPT bit must be
cleared by software.
0: No CPT interrupt occurred
1: CPT interrupt pending
Bit 5 = OTC:
Overflow of Tacho counter pending
bit.
This bit is set by hardware on a Tacho counter
overflow while OTCE=1. The OTC bit must be
cleared by software.
0: No OTC interrupt occurred
1: OTC interrupt pending
Bit 4 = ADT:
Automatic Data Transfer pending
bit.
This bit is set by hardware when data is trans-
ferred from the preload registers to the compare
registers while ADTE=1. The ADT bit must be
cleared by software.
0: No ADT interrupt occurred
1: ADT interrupt pending
Bit 3 = ZPC:
Zero of PWM counter pending bit.
This bit is set by hardware when the PWM counter
reaches zero while ZPCE=1. The ZPC bit must be
cleared by software.
0: No ZPC interrupt occurred
1: ZPC interrupt pending
Bit 2 = CPU:
Compare U pending bit.
In Classical Mode (CMS bit = 0), this bit is set by
hardware when the PWM Counter reaches the
Compare U register value while CPUE=1.
In Zerocentered Mode (CMS bit =1), this bit is set
by hardware when the PWM Counter reaches the
Compare U register value while CPUE=1 in up or
downcounting (depending on the UDIS bit in the
PSR register). The CPU bit must be cleared by
software.
0: No CPU interrupt occurred
1: CPU interrupt pending
Bit 1 = CPV:
Compare V pending bit.
In Classical Mode (CMS bit = 0), this bit is set by
hardware when the PWM Counter reaches the
Compare V register value while CPVE=1.
In Zerocentered Mode (CMS bit =1), this bit is set
by hardware when the PWM Counter reaches the
Compare V register value while CPVE=1 in up or
downcounting (depending on the UDIS bit in the
PSR register). The CPPRS register). The CPV bit
must be cleared by software.
0: No CPV interrupt occurred
1: CPV interrupt pending
Bit 0 = CPW:
Compare W pending bit.
In Classical Mode (CMS bit = 0), this bit is set by
hardware when the PWM Counter reaches the
Compare W register value while CPWE=1.
In Zerocentered Mode (CMS bit =1), this bit is set
by hardware when the PWM Counter reaches the
Compare W register value while CPWE=1 in up or
downcounting (depending on the UDIS bit in the
PSR register). The CPW bit must be cleared by
software.
0: No CPW interrupt occurred
1: CPW interrupt pending
Note 1: None of the bits in the IPR register can be
set by software, they can only be cleared.
Note 2: To clear the bits in the IPR register, the
user must not use direct addressing bit instruc-
tions such as AND, OR, BRES, etc. because some
interrupts may not be generated as expected. To
avoid this, do the following:
To clear one pending bit of the IPR register, load
the register with the mask corresponding to the bit
to be cleared.
For example:
To clear the CPW bit, use the instruction
LD R243,#1111 1110
rather than the instruction
AND R243,#1111 1110.
70
CM0
CPT
OTC
ADT
ZPC
CPU
CPV
CPW
9
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