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| 型号： | ST92E141K4D1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, UVPROM, 25 MHz, MICROCONTROLLER, CDIP32 |
| 封装： | WINDOWED, SHRINK, CERAMIC, DIP-32 |
| 文件页数： | 143/178页 |
| 文件大小： | 1097K |
| 代理商： | ST92E141K4D1 |
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ST92141 - RESET AND CLOCK CONTROL UNIT (RCCU)
CLOCK MANAGEMENT (Cont’d)
5.3.4 Low Power Modes
The user can select an automatic slowdown of
clock frequency during Wait for Interrupt opera-
tion, thus idling in low power mode while waiting
for an interrupt. In WFI operation the clock to the
CPU core (CPUCLK) is stopped, thus suspending
program execution, while the clock to the peripher-
als (INTCLK) may be programmed as described in
the following paragraphs. An example of Low
Power operation in WFI is illustrated in Figure 30.
If low power operation during WFI is disabled
(LPOWFI bit = 0 in the CLKCTL Register), the
CPU CLK is stopped but INTCLK is unchanged.
If low power operation during Wait for Interrupt is
enabled (LPOWFI bit = 1 in the CLKCTL Register),
as soon as the CPU executes the WFI instruction,
the PLL is turned off and the system clock will be
forced to CLOCK2 divided by 16, or to the external
low frequency clock, CK_AF divided by 16 if this
has been selected by setting WFI_CKSEL, and
providing CKAF_ST is set, thus indicating that the
external clock is selected and actually present on
the CK_AF pin. The division by 16 is only selected
by Hardware after entering Low Power WFI mode.
If the external clock source is used, the crystal os-
cillator may be stopped by setting the XTSTOP bit,
providing that the CK_AF clock is present and se-
lected, indicated by CKAF_ST being set. The crys-
tal oscillator will be stopped automatically on en-
tering WFI if the WFI_CKSEL bit has been set. It
should be noted that selecting a non-existent
CK_AF clock source is impossible, since such a
selection requires that the auxiliary clock source
be actually present and selected. In no event can
a non-existent clock source be selected inadvert-
ently.
It is up to the user program to switch back to a fast-
er clock on the occurrence of an interrupt, taking
care to respect the oscillator and PLL stabilisation
delays, as appropriate.It should be noted that any
of the low power modes may also be selected ex-
plicitly by the user program even when not in Wait
for Interrupt mode, by setting the appropriate bits.
5.3.5 Interrupt Generation
System clock selection modifies the CLKCTL and
CLK_FLAG registers.
The clock control unit generates an external inter-
rupt request when CK_AF and CLOCK2/16 are
selected or deselected as system clock source, as
well as when the system clock restarts after a stop
request (when the STOP MODE feature is availa-
ble on the specific device). This interrupt can be
masked by resetting the INT_SEL bit in the
CLKCTL register. In the RCCU the interrupt is
generated with a high to low transition (see inter-
rupt and DMA chapters for further information).
Table 14. Summary of Operating Modes using main Crystal Controlled Oscillator
MODE
INTCLK
CPUCLK
DIV2
PRS0-2
CSU_CKSEL
MX0-1
DX2-0
LPOWFI
XT_DIV16
PLL x BY 14
XTAL/2
x (14/D)
INTCLK/N
1
N-1
1
1 0
D-1
X
1
PLL x BY 10
XTAL/2
x (10/D)
INTCLK/N
1
N-1
1
0 0
D-1
X
1
PLL x BY 8
XTAL/2
x (8/D)
INTCLK/N
1
N-1
1
1 1
D-1
X
1
PLL x BY 6
XTAL/2
x (6/D)
INTCLK/N
1
N-1
1
0 1
D-1
X
1
SLOW 1
XTAL/2
INTCLK/N
1
N-1
X
111
X
1
SLOW 2
XTAL/32
INTCLK/N
1
N-1
X
0
WAIT FOR
INTERRUPT
If LPOWFI=0, no changes occur on INTCLK, but CPUCLK is stopped anyway.
LOW POWER
WAIT FOR
INTERRUPT
XTAL/32
STOP
1
X
1
RESET
XTAL/2
INTCLK
1
0
00
111
0
1
EXAMPLE
XTAL=4.4 MHz
2.2*10/2
= 11MHz
11MHz
1
0
1
00
001
X
1
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