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参数资料
型号： ST92E141K4D1
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 16-BIT, UVPROM, 25 MHz, MICROCONTROLLER, CDIP32
封装： WINDOWED, SHRINK, CERAMIC, DIP-32
文件页数： 135/178页
文件大小： 1097K
代理商： ST92E141K4D1
6/178
ST92141 - GENERAL DESCRIPTION
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST92141 microcontroller is developed and
manufactured by STMicroelectronics using a pro-
prietary n-well HCMOS process. Its performance
derives from the use of a flexible 256-register pro-
gramming model for ultra-fast context switching
and real-time event response. The intelligent on-
chip peripherals offload the ST9 core from I/O and
data management processing tasks allowing criti-
cal application tasks to get the maximum use of
core resources. The new-generation ST9 MCU
devices now also support low power consumption
and low voltage operation for power-efficient and
low-cost embedded systems.
1.1.1 ST9+ Core
The advanced Core consists of the Central
Processing Unit (CPU), the Register File, the Inter-
rupt controller, and the Memory Management Unit.
The MMU allows addressing of up to 4 Megabytes
of program and data mapped into a single linear
space.
Four independent buses are controlled by the
Core: a 16-bit memory bus, an 8-bit register data
bus, an 8-bit register address bus and a 6-bit inter-
rupt bus which connects the interrupt controllers in
the on-chip peripherals with the core.
Note: The DMA features of the ST9+ core are not
used by the on-chip peripherals of the ST92141.
This multiple bus architecture makes the ST9 fam-
ily devices highly efficient for accessing on and off-
chip memory and fast exchange of data with the
on-chip peripherals.
The general-purpose registers can be used as ac-
cumulators, index registers, or address pointers.
Adjacent register pairs make up 16-bit registers for
addressing or 16-bit processing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit opera-
tions, including arithmetic, loads/stores, and mem-
ory/register and memory/memory exchanges.
1.1.2 Power Saving Modes
To optimize performance versus power consump-
tion, a range of operating modes can be dynami-
cally selected by software according to the re-
quirements of the application.
Run Mode. This is the full speed execution mode
with CPU and peripherals running at the maximum
clock speed delivered either by the Phase Locked
Loop controlled by the RCCU (Reset and Clock
Control Unit), directly by the oscillator or by an ex-
ternal source (dedicated Pin or Alternate Func-
tion).
Slow Mode. Power consumption can be signifi-
cantly reduced by running the CPU and the periph-
erals at reduced clock speed using the CPU Pres-
caler and RCCU Clock Divider.
Wait For Interrupt Mode. The Wait For Interrupt
(WFI) instruction suspends program execution un-
til an interrupt request is acknowledged. During
WFI, the CPU clock is halted while the peripheral
with interrupt capability and interrupt controller are
kept running at a frequency that can be pro-
grammed by software in the RCCU registers. In
this mode, the power consumption of the device
can be reduced by more than 95% (Low Power
WFI).
Halt Mode. When executing the HALT instruction,
and if the Watchdog is not enabled, the CPU and
its peripherals stop operating. If however the
Watchdog is enabled, the HALT instruction has no
effect. The main difference between Halt mode
and Stop mode is that a reset is necessary to exit
from Halt mode which causes the system to be
reinitialized.
Stop Mode. When Stop mode is requested by ex-
ecuting the STOP sequence (see Wake-up Man-
agement Unit section), the CPU and the peripher-
als stop operating. Operations resume after a
wake-up line is activated. The difference between
Stop mode and Halt mode is in the way the CPU
exits each state: when the STOP sequence is ex-
ecuted, the status of the registers is recorded, and
when the system exits from Stop mode the CPU
continues execution with the same status, without
a system reset.
The Watchdog counter, if enabled, is stopped. Af-
ter exiting Stop mode it restarts counting from
where it left off.
When the MCU exits from STOP mode, the oscil-
lator, which was also sleeping, requires a start-up
time to restart working properly. An internal coun-
ter is present to guarantee that, after exiting Stop
Mode, all operations take place with the clock sta-
bilised.
1.1.3 System Clock
A programmable PLL Clock Generator allows
standard 3 to 5 MHz crystals to be used to obtain a
large range of internal frequencies up to 25MHz.
9
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