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参数资料
型号： ST92E141K4D1
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 16-BIT, UVPROM, 25 MHz, MICROCONTROLLER, CDIP32
封装： WINDOWED, SHRINK, CERAMIC, DIP-32
文件页数： 56/178页
文件大小： 1097K
代理商： ST92E141K4D1
149/178
ST92141 - ANALOG TO DIGITAL CONVERTER (ADC)
ANALOG TO DIGITAL CONVERTER (Cont’d)
On devices where two A/D Converters are present
they can be triggered from the same source.
7.6.2.3 Analog Watchdogs
Two internal Analog Watchdogs are available for
highly flexible automatic threshold monitoring of
external analog signal levels.
Analog channels 6 and 7 monitor an acceptable
voltage level window for the converted analog in-
puts. The external voltages applied to inputs 6 and
7 are considered normal while they remain below
their respective Upper thresholds, and above or at
their respective Lower thresholds.
When the external signal voltage level is greater
than, or equal to, the upper programmed voltage
limit, or when it is less than the lower programmed
voltage limit, a maskable interrupt request is gen-
erated and the Compare Results Register is up-
dated in order to flag the threshold (Upper or Low-
er) and channel (6 or 7) responsible for the inter-
rupt. The four threshold voltages are user pro-
grammable in dedicated registers (08h to 0Bh) of
the ADC register page. Only the 4 MSBs of the
Compare Results Register are used as flags, each
of the four MSBs being associated with a threshold
condition.
Following a reset, these flags are reset. During
normal ADC operation, the CRR bits are set, in or-
der to flag an out of range condition and are auto-
matically reset by hardware after a software reset
of the Analog Watchdog Request flag in the ICR
Register.
7.6.2.4 Power Down Mode
Before enabling an A/D conversion, the POW bit of
the Control Logic Register must be set; this must
be done at least 60
s before the first conversion
start, in order to correctly bias the analog section
of the converter circuitry.
When the ADC is not required, the POW bit may
be reset in order to reduce the total power con-
sumption. This is the reset configuration, and this
state is also selected automatically when the ST9
is placed in Halt Mode (following the execution of
the halt instruction).
Figure 78. A/D Trigger Source
Converter
External Trigger
On Chip Event
(Internal trigger)
A/D 0
EXTRG pin
MFT 0
A/D 1
Analog Voltage
Upper threshold
Lower threshold
Normal Area
(Window Guarded)
9
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