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| 型号： | TMDXBDKFP5515 |
| 厂商： | Texas Instruments |
| 文件页数： | 109/159页 |
| 文件大小： | 0K |
| 描述： | KIT DEV FINGERPRINT C5515 |
| 标准包装： | 1 |
| 传感器类型： | 指纹 |
| 接口： | USB |
| 电源电压： | 5V |
| 嵌入式： | 是，MCU，16 位 |
| 已供物品： | 板，扩展板，线缆，迷你型 DVD，传感器 |
| 已用 IC / 零件： | C5515 |
| 产品目录页面： | 718 (CN2011-ZH PDF) |
| 其它名称： | 296-27452 |
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SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
Power Down Sequence:
1. CPU must set the LDO_PD bit or the BG_PD bit in the RTCPMGT register (See Figure 5-26 ). Once
the LDO_PD bit or the BG_PD bit is set to 1, the DSP_LDOO will be internally shut off and it will cause
the internal POR holds the internal POWERGOOD signal low, which creates isolation for RTC.
2. All of the device power domains can be shut down except RTC Core (CVDDRTC), RTC I/O
(DVDDRTC), and LDO inputs (LDOI).
Wake-Up Sequence:
1. When waking up the device, all power domains must be turned back on before or upon applying a
pulse to WAKEUP.
2. A pulse ( ≥ 30.5 μs) must be applied to the WAKEUP pin (active high). When the WAKEUP pin is
asserted, the voltage on the DSP_LDOO pin will start ramping up at the positive level of WAKEUP and
it is monitored by the internal POR. Until the voltage reaches to the threshold level, the internal POR
will hold the internal POWERGOOD signal low, which provides isolation to RTC during transition
period. Once the voltage reaches to the threshold level, the internal POR asserts the internal
POWERGOOD signal (logic level high) and it resets reset of the system and disables RTC isolation
and enables CPU to communicate with RTC.
Figure 5-26. RTC Power Management Register (RTCPMGT) [1930h]
15
Reserved
R-0
8
7
Reserved
R-0
5
4
WU_DOUT
R/W-1
3
WU_DIR
R/W-0
2
BG_PD
R/W-0
1
LDO_PD
R/W-0
0
RTCCLKOUTEN
R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 5-24. RTCPMGT Register Bit Descriptions
BIT
15:5
4
3
2
NAME
RESERVED
WU_DOUT
WU_DIR
BG_PD
DESCRIPTION
Reserved. Read-only, writes have no effect.
Wakeup output, active low/open-drain.
0 = WAKEUP pin driven low.
1 = WAKEUP pin is in high-impedance (Hi-Z).
Wakeup pin direction control.
0 = WAKEUP pin configured as a input.
1 = WAKEUP pin configured as a output.
Note: When the WAKEUP pin is configured as an input, it is active high. When the WAKEUP pin is
configured as an output, is an open-drain that is active low and should be externally pulled-up via a
10-k Ω resistor to DV DDRTC . WU_DIR must be configured as an input to allow the WAKEUP pin to
wake the device up from idle modes.
Bandgap, on-chip LDOs, and the analog POR power down bit.
This bit shuts down the on-chip LDOs (ANA_LDO, DSP_LDO, and USB_LDO), the Analog POR,
and Bandgap reference. BG_PD and LDO_PD are only intended to be used when the internal
LDOs supply power to the chip. If the internal LDOs are bypassed and not used then the BG_PD
and LDO_PD power down mechanisms should not be used since POR gets powered down and the
POWERGOOD signal is not generated properly.
After this bit is asserted, the on-chip LDOs, Analog POR, and the Bandgap reference can be re-
enabled by the WAKEUP pin (high) or the RTC alarm interrupt. The Bandgap circuit will take about
100 msec to charge the external 0.1 uF capacitor via the internal 326-k Ω resistor.
0 = On-chip LDOs, Analog POR, and Bandgap reference are enabled.
1 = On-chip LDOs, Analog POR, and Bandgap reference are disabled (shutdown).
Copyright ? 2010–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Product Folder Links: TMS320C5515
109
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