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| 型号： | TMDXBDKFP5515 |
| 厂商： | Texas Instruments |
| 文件页数： | 58/159页 |
| 文件大小： | 0K |
| 描述： | KIT DEV FINGERPRINT C5515 |
| 标准包装： | 1 |
| 传感器类型： | 指纹 |
| 接口： | USB |
| 电源电压： | 5V |
| 嵌入式： | 是，MCU，16 位 |
| 已供物品： | 板，扩展板，线缆，迷你型 DVD，传感器 |
| 已用 IC / 零件： | C5515 |
| 产品目录页面： | 718 (CN2011-ZH PDF) |
| 其它名称： | 296-27452 |
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SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
3.6
3.6.1
Configurations After Reset
The following sections provide details on configuring the device after reset. Multiplexed pin functions are
selected by software after reset. For more details on multiplexed pin function control, see Section 3.7 ,
Multiplexed Pin Configurations .
External Bus Selection Register (EBSR)
The External Bus Selection Register (EBSR) determines the mapping of the LCD controller, I2S2, I2S3,
UART, SPI, and GPIO signals to 21 signals of the external parallel port pins. It also determines the
mapping of the I2S or MMC/SD ports to serial port 1 pins and serial port 2 pins. The EBSR register is
located at port address 0x1C00. Once the bit fields of this register are changed, the routing of the signals
takes place on the next CPU clock cycle.
Additionally, the EBSR controls the function of the upper bits of the EMIF address bus. Pins
EM_A[20:15]/GP[26:21] can be individually configured as GPIO pins through the Axx_MODE bits. When
Axx_MODE = 1, the EM_A[xx] pin functions as a GPIO pin. When Axx_MODE = 0, the EM_A[xx] pin
retains its EMIF functionality.
Before modifying the values of the external bus selection register, you must clock gate all affected
peripherals through the Peripheral Clock Gating Control Register. After the external bus selection register
has been modified, you must reset the peripherals before using them through the Peripheral Software
Reset Counter Register.
Figure 3-3. External Bus Selection Register (EBSR) [1C00h]
15
14
12
11
10
9
8
Reserved
R-0
PPMODE
R/W-000
SP1MODE
R/W-00
SP0MODE
R/W-00
7
Reserved
R-0
6
Reserved
R-0
5
A20_MODE
R/W-0
4
A19_MODE
R/W-0
3
A18_MODE
R/W-0
2
A17_MODE
R/W-0
1
A16_MODE
R/W-0
0
A15_MODE
R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 3-5. EBSR Register Bit Descriptions
BIT
15
14:12
NAME
RESERVED
PPMODE
DESCRIPTION
Reserved. Read-only, writes have no effect.
Parallel Port Mode Control Bits. These bits control the pin multiplexing of the LCD Controller, SPI,
LCD Controller, SPI, UART, I2S2, I2S3, and GP[31:27, 20:18] Pin Multiplexing .
000 = Mode 0 (16-bit LCD Controller). All 21 signals of the LCD Bridge module are routed to the 21
external signals of the parallel port.
001 = Mode 1 (SPI, GPIO, UART, and I2S2). 7 signals of the SPI module, 6 GPIO signals, 4
signals of the UART module and 4 signals of the I2S2 module are routed to the 21 external signals
of the parallel port.
010 = Mode 2 (8-bit LCD Controller and GPIO). 8-bits of pixel data of the LCD Controller module
and 8 GPIO are routed to the 21 external signals of the parallel port.
011 = Mode 3 (8-bit LCD Controller, SPI, and I2S3). 8-bits of pixel data of the LCD Controller
module, 4 signals of the SPI module, and 4 signals of the I2S3 module are routed to the 21 external
signals of the parallel port.
100 = Mode 4 (8-bit LCD Controller, I2S2, and UART). 8-bits of pixel data of the LCD Controller
module, 4 signals of the I2S2 module, and 4 signals of the UART module are routed to the 21
external signals of the parallel port.
101 = Mode 5 (8-bit LCD Controller,SPI, and UART). 8-bits of pixel data of the LCD Controller
module, 4 signals of the SPI module, and 4 signals of the UART module are routed to the 21
external signals of the parallel port.
110 = Mode 6 (SPI, I2S2, I2S3, and GPIO). 7 signals of the SPI module, 4 signals of the I2S2
module, 4 signals of the I2S3 module, and 6 GPIO are routed to the 21 external signals of the
parallel port.
111 = Reserved.
58
Device Configuration
Product Folder Links: TMS320C5515
Copyright ? 2010–2013, Texas Instruments Incorporated
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