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| 型号： | TMDXBDKFP5515 |
| 厂商： | Texas Instruments |
| 文件页数： | 54/159页 |
| 文件大小： | 0K |
| 描述： | KIT DEV FINGERPRINT C5515 |
| 标准包装： | 1 |
| 传感器类型： | 指纹 |
| 接口： | USB |
| 电源电压： | 5V |
| 嵌入式： | 是，MCU，16 位 |
| 已供物品： | 板，扩展板，线缆，迷你型 DVD，传感器 |
| 已用 IC / 零件： | C5515 |
| 产品目录页面： | 718 (CN2011-ZH PDF) |
| 其它名称： | 296-27452 |
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SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
3.4
Boot Sequence
The boot sequence is a process by which the device's on-chip memory is loaded with program and data
sections from an external image file (in flash memory, for example). The boot sequence also allows,
optionally, for some of the device's internal registers to be programmed with predetermined values. The
boot sequence is started automatically after each device reset. For more details on device reset, see
There are several methods by which the memory and register initialization can take place. Each of these
methods is referred to as a boot mode. At reset, the device cycles through different boot modes until an
image is found with a valid boot signature. The on-chip Bootloader allows the DSP registers to be
configured during the boot process, if the optional register configuration section is present in the boot
image (see Figure 3-2 ). For more information on the boot modes supported, see Section 3.4.1 , Boot
Modes .
1. Immediately after reset, the CPU fetches the reset vector from 0xFFFF00. MP/MC is 0 by default, so
0xFFFF00 is mapped to internal ROM. The PLL is in bypass mode.
2. Set CLKOUT slew rate control to slow slew rate.
3. Idle all peripherals, MPORT and HWA.
4. If CLK_SEL = 0, the Bootloader powers up the PLL and sets its output frequency to 12.288 MHz (with
a 375x multiplier using VP = 749, VS = 0, input divider disabled, output divide-by-8 enabled, and output
divider enabled with VO = 0). If CLK_SEL = 1, the Bootloader keeps the PLL bypassed.
5. Apply manufacturing trim to the bandgap references.
6. Disable CLKOUT.
7. Test for NOR boot on all asynchronous CS spaces (EM_CS[2:5]) with 16-bit access:
(a) Check the first 2 bytes read from boot signature.
(b) If the boot signature is not valid, go to step 8.
(c) Set Register Configuration, if present in boot image.
(d) Attempt NOR boot, go to step 17.
8. Test for NAND boot on all asynchronous CS spaces (EM_CS[2:5]) with 8-bit access:
(a) Check the first 2 bytes read from boot table for a boot signature match.
(b) If the boot signature is not valid, go to step 9.
(c) Set Register Configuration, if present in boot image.
(d) Attempt NAND boot, go to step 17.
9. Test for 16-bit and 24-bit SPI EEPROM boot on SPI_CS[0] with 500-KHz clock rate and for Parallel
Port Mode on External bus Selection Register set to 5, then set to 6:
(a) Check the first 2 bytes read from boot table for a boot signature match using 16-bit address mode.
(b) If the boot signature is not valid, read the first 2 bytes again using 24-bit address mode.
(c) If the boot signature is not valid from either case (16-bit and 24-bit address modes), go to step 10.
(d) Set Register Configuration, if present in boot image.
(e) Attempt SPI Serial Memory boot, go to step 17.
10. Test for I2C EEPROM boot with a 7-bit slave address 0x50 and 400-kHz clock rate.
(a) Check the first 2 bytes read from boot table for a boot signature match.
(b) If the boot signature is not valid, go to step 11.
(c) Set Register Configuration, if present in boot image.
(d) Attempt I2C EEPROM boot, go to step 17.
11. Test for MMC/SD boot — For more information on MMC/SD boot, contact your local sales
representative.
12. Set the PLL output to approximately 36 MHz. If CLK_SEL = 1, CLKIN multiplied by 3x, ; if CLK_SEL =
0, CLKIN is multiplied by 1125x.
13. Test for USB boot — For more information on USB boot, contact your local sales representative.
54
Device Configuration
Product Folder Links: TMS320C5515
Copyright ? 2010–2013, Texas Instruments Incorporated
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