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参数资料
型号： TMS320F241PGS
厂商： TEXAS INSTRUMENTS INC
元件分类： 数字信号处理
英文描述： 0-BIT, 5 MHz, OTHER DSP, PQFP64
封装： PLASTIC, QFP-64
文件页数： 30/122页
文件大小： 1465K
代理商： TMS320F241PGS
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064D DECEMBER 1997 REVISED FEBRUARY 2006
15
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Terminal Functions - F241 PG and FN Packages
NAME
64
QFP
68
PLCC
TYPE
RESET
STATE
DESCRIPTION
NAME
NO.
TYPE
STATE
DESCRIPTION
ANALOG-TO-DIGITAL CONVERTER (ADC) INPUTS
ADCIN00
24
32
ADCIN01
23
31
ADCIN02
22
30
ADCIN03
21
29
I
Analog inputs to the ADC
ADCIN04
20
28
I
Analog inputs to the ADC
ADCIN05
19
26
ADCIN06
18
25
ADCIN07
15
22
VCCA
14
21
Analog supply voltage for ADC (5 V). It is highly recommended to isolate
VCCA from the digital supply voltage (and VSSA from digital ground) to
maintain the specified accuracy and improve the noise immunity of the
ADC.
VSSA
13
20
Analog ground reference for ADC
VREFHI
16
23
ADC analog high-voltage reference input
VREFLO
17
24
ADC analog low-voltage reference input
EVENT MANAGER
T1CMP/T1PWM/IOPB4
12
19
I/O/Z
Timer 1 compare output/general-purpose bidirectional digital I/O (GPIO).
T2CMP/T2PWM/IOPB5
11
18
I/O/Z
Timer 2 compare output/GPIO
TDIR/IOPB6
56
67
I/O
Counting direction for GP timer/GPIO. If TDIR=1, upward counting is
selected. If TDIR=0, downward counting is selected.
TCLKIN/IOPB7
57
68
I/O
External clock input for GP timer/GPIO. Note that timer can also use the
internal device clock.
CAP1/QEP0/IOPA3
8
15
I/O
Capture input #1/quadrature encoder pulse input #0/GPIO
CAP2/QEP1/IOPA4
7
14
I/O
I
Capture input #2/quadrature encoder pulse input #1/GPIO
CAP3/IOPA5
6
13
I/O
I
Capture input #3/GPIO
PWM1/IOPA6
64
7
I/O/Z
Compare/PWM output pin #1 or GPIO
PWM2/IOPA7
63
6
I/O/Z
Compare/PWM output pin #2 or GPIO
PWM3/IOPB0
62
5
I/O/Z
Compare/PWM output pin #3 or GPIO
PWM4/IOPB1
61
4
I/O/Z
Compare/PWM output pin #4 or GPIO
PWM5/IOPB2
60
3
I/O/Z
Compare/PWM output pin #5 or GPIO
PWM6/IOPB3
59
2
I/O/Z
Compare/PWM output pin #6 or GPIO
PDPINT
58
1
I
Power drive protection interrupt input. This interrupt, when activated, puts
the PWM output pins in the high-impedance state, should motor
drive/power converter abnormalities, such as overvoltage or overcurrent,
etc., arise. PDPINT is level-sensitive and can cause multiple interrupts
when held low.
I = input, O = output, Z = high impedance
The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.
NOTE: Bold, italicized pin names indicate pin function after reset.
LEGEND:
↑ Internal pullup
↓ Internal pulldown
(Typical active pullup/pulldown value is 150
A.)
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