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参数资料
| 型号： | TMS320F241PGS |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 5 MHz, OTHER DSP, PQFP64 |
| 封装： | PLASTIC, QFP-64 |
| 文件页数： | 31/122页 |
| 文件大小： | 1465K |
| 代理商： | TMS320F241PGS |
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TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064D DECEMBER 1997 REVISED FEBRUARY 2006
16
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Terminal Functions - F241 PG and FN Packages (Continued)
NAME
64
QFP
68
PLCC
TYPE
RESET
STATE
DESCRIPTION
NAME
NO.
TYPE
STATE
DESCRIPTION
SERIAL PERIPHERAL INTERFACE (SPI) AND BIT I/O PINS
SPISIMO/IOPC2
45
56
I/O
SPI slave in, master out or GPIO
SPISOMI/IOPC3
46
57
I/O
I
SPI slave out, master in or GPIO
SPICLK/IOPC4
47
58
I/O
I
SPI clock or GPIO
SPISTE/IOPC5
48
59
I/O
SPI slave transmit enable (optional) or GPIO
SERIAL COMMUNICATIONS INTERFACE (SCI) AND BIT I/O PINS
SCITXD/IOPA0
43
54
I/O
I
SCI asynchronous serial port transmit data or GPIO
SCIRXD/IOPA1
44
55
I/O
I
SCI asynchronous serial port receive data or GPIO
CONTROLLER AREA NETWORK (CAN)
CANTX/IOPC6
4
11
I/O
I
CAN transmit data or GPIO
CANRX/IOPC7
3
10
I/O
I
CAN receive data or GPIO
INTERRUPT, EXTERNAL ACCESS, AND MISCELLANEOUS SIGNALS
RS
27
35
I/O
I
Device reset. RS causes the F243/241 to terminate execution and sets
PC = 0. When RS is brought to a high level, execution begins at location
zero of program memory. RS affects (or sets to zero) various registers
and status bits. When the watchdog timer overflows, it initiates a system
reset pulse reflected on the RS pin. This pulse is eight clock cycles wide.
NMI
53
64
I
Nonmaskable interrupt. When NMI is activated, the device is interrupted
regardless of the state of the INTM bit of the status register. NMI is
(falling) edge- and low-level-sensitive. To be recognized by the core, this
pin must be kept low for at least one clock cycle after the falling edge.
XINT1/IOPA2
55
66
I/O
I
External user interrupt 1 or GPIO. Both XINT1 and XINT2 are edge-
sensitive. To be recognized by the core, these pins must be kept low/high
for at least one clock cycle after the edge. The edge polarity is
programmable.
XINT2/ADCSOC/IOPD1
54
65
I/O
I
External user interrupt 2. External “start-of-conversion” input for
ADC/GPIO. Both XINT1 and XINT2 are edge-sensitive. To be
recognized by the core, these pins must be kept low/high for at least one
clock cycle after the edge. The edge polarity is programmable.
XF/IOPC0
39
50
I/O
O 1
External flag output (latched software-programmable signal). XF is a
general-purpose output pin. It is set/reset by the SETC XF/CLRC XF
instruction. This pin is configured as an external flag output by all device
resets. It can be used as a GPIO, if not used as XF.
BIO/IOPC1
42
53
I/O
I
Branch control input. BIO is polled by the BCND pma,BIO instruction. If
BIO is low, a branch is executed. If BIO is not used, it should be pulled
high. This pin is configured as a branch control input by all device resets.
It can be used as a GPIO, if not used as a branch control input.
PMT
49
60
I
Enables parallel module test (PMT). This pin must be connected to
ground.
I = input, O = output, Z = high impedance
The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.
NOTE: Bold, italicized pin names indicate pin function after reset.
LEGEND:
↑ Internal pullup
↓ Internal pulldown
(Typical active pullup/pulldown value is 150
A.)
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| TMS320F28015PZQ | 功能描述:数字信号处理器和控制器 - DSP, DSC 32-Bit DSC w/ 32KB Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
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