参数资料
型号: TMS320F241PGS
厂商: TEXAS INSTRUMENTS INC
元件分类: 数字信号处理
英文描述: 0-BIT, 5 MHz, OTHER DSP, PQFP64
封装: PLASTIC, QFP-64
文件页数: 32/122页
文件大小: 1465K
代理商: TMS320F241PGS
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064D DECEMBER 1997 REVISED FEBRUARY 2006
17
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Terminal Functions - F241 PG and FN Packages (Continued)
NAME
64
QFP
68
PLCC
TYPE
RESET
STATE
DESCRIPTION
NAME
NO.
TYPE
STATE
DESCRIPTION
CLOCK SIGNALS
XTAL1/CLKIN
35
46
I
PLL oscillator input pin. Crystal input to PLL/clock source input to PLL.
XTAL1/CLKIN is tied to one side of a reference crystal.
XTAL2
36
47
O
Crystal output. PLL oscillator output pin. XTAL2 is tied to one side of a
reference crystal. This pin goes in the high-impedance state when
EMU1/OFF is active low.
CLKOUT/IOPD0
5
12
I/O
O
Clock output. This pin outputs either the CPU clock (CLKOUT) or the
watchdog clock (WDCLK). The selection is made by the CLKSRC bit (bit 14)
of the System Status and Control Register (SSCR). This pin can be used as
a GPIO if not used as a clock output pin.
TEST SIGNALS
TCK
28
36
I
JTAG test clock with internal pullup
(
↑)
TDI
29
37
I
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected
register (instruction or data) on a rising edge of TCK.
(
↑)
TDO
30
38
I/O
I
JTAG scan out, test data output (TDO). The contents of the selected register
(instruction or data) is shifted out of TDO on the falling edge of TCK.
(
↓)
TMS
31
39
I
JTAG test-mode select (TMS) with internal pullup. This serial control input is
clocked into the TAP controller on the rising edge of TCK.
(
↑)
TRST
32
40
I
JTAG test reset with internal pulldown. TRST, when driven high, gives the
scan system control of the operations of the device. If this signal is not
connected or driven low, the device operates in its functional mode, and the
test reset signals are ignored.
(
↓)
EMU0
37
48
I/O
I
Emulator I/O pin 0 with internal pullup. When TRST is driven high, this pin is
used as an interrupt to or from the emulator system and is defined as
input/output through the JTAG scan.
(
↑)
EMU1
38
49
I/O
I
Emulator I/O pin 1 with internal pullup. When TRST is driven high, this pin is
used as an interrupt to or from the emulator system and is defined as
input/output through JTAG scan.
(
↑)
SUPPLY SIGNALS
VDD
9
16
Digital logic supply voltage (5 V)
VDD
41
52
Digital logic supply voltage (5 V)
42
VDDO
1
8
Digital logic and buffer supply voltage (5 V)
VDDO
34
45
Digital logic and buffer supply voltage (5 V)
51
62
41
VSS
10
17
Digital logic ground reference
VSS
40
51
Digital logic ground reference
I = input, O = output, Z = high impedance
The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.
NOTE: Bold, italicized pin names indicate pin function after reset.
LEGEND:
↑ Internal pullup
↓ Internal pulldown
(Typical active pullup/pulldown value is 150
A.)
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