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| 型号： | TMS320F241PGS |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 5 MHz, OTHER DSP, PQFP64 |
| 封装： | PLASTIC, QFP-64 |
| 文件页数： | 72/122页 |
| 文件大小： | 1465K |
| 代理商： | TMS320F241PGS |
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TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064D DECEMBER 1997 REVISED FEBRUARY 2006
53
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
analog-to-digital converter (ADC) module
A simplified functional block diagram of the ADC module is shown in Figure 11. The ADC module consists of
a 10-bit ADC with a built-in sample-and-hold (S/ H) circuit. A total of 8 analog input channels is available on the
F243/F241. Eight analog inputs are provided by way of an 8-to-1 analog multiplexer. Maximum total conversion
time for each ADC unit is 1
s. Reference voltage for the ADC module is 05 V and is supplied externally.
Functions of the ADC module include:
D The ADC unit can perform single or continuous S/H and conversion operations. When in continuous
conversion mode, the ADC generates two results every 1700 ns (with a 20-MHz clock and a prescale factor
of 1). These two results can be two separate analog inputs.
D Two 2-level-deep FIFO result registers
D Conversion can be started by software, an external signal transition on a device pin (ADCSOC), or by
certain event manager events.
D The ADC control register is double-buffered (with a shadow register) and can be written to at any time. A
new conversion can start either immediately or when the previous conversion process is completed.
D In single-conversion mode, at the end of each conversion, an interrupt flag is set and the peripheral interrupt
request (PIRQ) is generated if it is unmasked/enabled.
D The result of previous conversions stored in data registers will be lost when a third result is stored in the
2-level-deep data FIFO.
A/D overview
The “pseudo” dual ADC is based around a 10-bit string/capacitor converter with the switched capacitor string
providing an inherent S / H function. (Note: There is only one converter with only one inherent S/H circuit.) This
peripheral behaves as though there are two analog converters, ADC #1 and ADC #2, but in fact, it uses only
one converter. This feature makes the A/D software compatible with the C240’s A/D and also allows two values
(e.g., voltage and current) to be converted almost simultaneoulsy with one conversion request. VCCA and VSSA
pins must be connected to 5 V and analog ground, respectively. Standard isolation techniques must be used
while applying power to the ADC module.
The ADC module, shown in Figure 11, has the following features:
D Up to 8 analog inputs, ADCIN00ADCIN07. The results from converting the inputs ADCIN00ADCIN07 are
placed in one of the ADCFIFO results registers (see Table 16). The digital value of the input analog voltage
is derived by:
Digital Value
+ 1023
Input Analog Voltage
* V
REFLO
V
REFHI
* V
REFLO
D Almost simultaneous measurement of two analog inputs, 1700 ns apart
D Single conversion and continuous conversion modes
D Conversion can be started by software, an internal event, and/or an external event.
D VREFHI and VREFLO (high- and low-voltage) reference inputs
D Two-level-deep digital result registers that contain the digital vaules of completed conversions
D Two programmable ADC module control registers (see Table 16)
D Programmable clock prescaler
D Interrupt or polled operation
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