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参数资料
型号： TMS320F241PGS
厂商： TEXAS INSTRUMENTS INC
元件分类： 数字信号处理
英文描述： 0-BIT, 5 MHz, OTHER DSP, PQFP64
封装： PLASTIC, QFP-64
文件页数： 86/122页
文件大小： 1465K
代理商： TMS320F241PGS
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064D DECEMBER 1997 REVISED FEBRUARY 2006
66
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
instruction set summary (continued)
Table 19. TMS320x24x Opcode Symbols
SYMBOL
DESCRIPTION
A
Address
ACC
Accumulator
ACCB
Accumulator buffer
ARx
Auxiliary register value (0 7)
BITx
4-bit field that specifies which bit to test for the BIT instruction
BMAR
Block-move address register
DBMR
Dynamic bit-manipulation register
I
Addressing-mode bit
II...II
Immediate operand value
INTM
Interrupt-mode flag bit
INTR#
Interrupt vector number
K
Constant
PREG
Product register
PROG
Program memory
RPTC
Repeat counter
SHF, SHFT
3/4-bit shift value
TC
Test-control bit
T P
Two bits used by the conditional execution instructions to represent the conditions TC, NTC, and BIO.
T P
Meaning
0 0
BIO low
0 1
TC = 1
1 0
TC = 0
1 1
None of the above conditions
TREGn
Temporary register n (n = 0, 1, or 2)
Z L V C
4-bit field representing the following conditions:
Z:
ACC = 0
L:
ACC < 0
V:
Overflow
C:
Carry
A conditional instruction contains two of these 4-bit fields. The 4-LSB field of the instruction is a 4-bit mask field. A 1 in the
corresponding mask bit indicates that the condition is being tested. The second 4-bit field (bits 4 7) indicates the state of
the conditions designated by the mask bits as being tested. For example, to test for ACC
≥ 0, the Z and L fields are set while
the V and C fields are not set. The next 4-bit field contains the state of the conditions to test. The Z field is set to indicate
testing of the condition ACC = 0, and the L field is reset to indicate testing of the condition ACC
≥ 0. The conditions possible
with these 8 bits are shown in the BCND and CC instructions. To determine if the conditions are met, the 4-LSB bit mask
is ANDed with the conditions. If any bits are set, the conditions are met.
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