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| 型号： | TS-MAC-SC-UT4 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 21/66页 |
| 文件大小： | 0K |
| 描述： | SITE LICENSE ETH MAC TRI SC/SCM |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | TSMACSCUT4 |
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Lattice Semiconductor
Functional Description
By default, the Rx MAC is configured to filter and discard Broadcast frames (i.e. all bits of the received DA == 1)
and multicast frames (i.e. bit[0] of the received DA == 1). The MAC can be configured to receive broadcast frames
by setting bit [7] of the TX_RX_CTL register.
Multicast frames are received only when bit [4] of the TX_RX_CTL register is set. When set, multicast frames are
subject to filtering that is dependent on a 64-bit hash table lookup. The 64-bit hash table is organized as eight, 8-bit
registers. The six middle bits of the most significant byte of the CRC calculated for the destination address field of
the frame, are used to address one of the 64 bits of the hash table. The three most significant bits of the calculated
CRC select one of the eight tables, and the three least significant bits select a bit. The frame is received only if the
retrieved bit is set. The IP core registers specifying the hash tables contents are described in “Internal Registers”
on page 25 . An example of C programming language code that can be used to determine hash table contents
based on the multicast addresses to be received is given in “Code Listing for Multicast Bit Selection Hash Algorithm
All other regular frames are filtered based on the Rx MAC address programmed into the MAC_ADDR_0,
MAC_ADDR_1 and MAC_ADDR_2 registers.
Filtering Based on Frame Length
The default minimum Ethernet frame size is 64 bytes. Any frame smaller than 64 bytes could possibly be a collision
fragment. By default, the Rx MAC is configured to ignore bytes shorter than 64 bytes. The user can configure the
MAC to receive shorter frames by setting bit [8] of the TX_RX_CTL register. Whenever a short frame is received,
the appropriate bit is set in the statistics vector, marking it as a Short frame.
The Rx MAC has been designed to receive frames larger than the standard specified maximum as easily as any
other frame. This ensures the MAC can work in environments that can generate jumbo frames. However, for statis-
tics purposes, the user can set the maximum length of the frame in the MAX_PKT_SIZE register. When a received
frame is larger than the number in this register, bit [31] of the Receive Statistics Vector bus is set, marking it as a
Long frame.
Receiving a PAUSE Frame
When the Rx MAC receives a PAUSE frame, the Tx MAC continues with the current transmission, then pauses for
the duration indicated in the PAUSE time. During this time, the Tx MAC can transmit Control frames.
Although PAUSE frames may contain the Multicast Address, Multicast filtering rules do not apply to them. If bit [3]
of the TX_RX_CTL register is set, the Rx MAC will signal the Tx MAC to stop transmitting for the duration specified
in the frame. If this bit is reset, the Rx MAC assumes the Tx MAC does not have the PAUSE capability and/or does
not wish to be paused and will not signal it to stop transmitting. If the drop control, bit[6] in the TX_RX_CTL register,
is set then the PAUSE frame is received but dropped internal to the MAC and is not transferred to the client FIFO
interface. Otherwise, the PAUSE frame is received and transferred to the FIFO.
Statistics Vector
By default, a Statistics Vector is generated for all received frames transferred to the external FIFO. If the user wants
the Rx MAC to ignore all incoming frames, then the input signal ignore_next_pkt must be asserted. In this case, a
frame that should have been received is ignored and the Rx MAC sets the Packet Ignored bit (bit 26) of the Statis-
tics Vector.
The MAX_PKT_SIZE register is programmed by the user as a threshold for setting the Long Frame bit of the Statis-
tics Vector. This value is used for un-tagged frames only. The Receive MAC will add “4” to the value specified in this
register for all VLAN tagged frames when checking against the number of bytes received in the frame. This is
because all VLAN tagged frames have an additional four bytes of data.
When a tagged frame is received, the entire VLAN tag field is stored in the VLAN_TAG register. Additionally, every
time a statistics vector is generated, some of the bits are written into the corresponding bit locations [9:1] of the
TX_RX_STS register. This is done so the user can get this information via the Host interface.
IPUG51_03.0, December 2010
21
Tri-Speed Ethernet MAC User’s Guide
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| VI-J0T-EZ-F4 | CONVERTER MOD DC/DC 6.5V 25W |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TSMACX2U2 | 功能描述:以太网模块 TriSpd Ethernet MAC RoHS:否 制造商:Lantronix 产品:Device Servers 数据速率:300 bps to 921.6 kbps, 10 Mbps, 100 Mbps 接口类型:Ethernet, Serial 工作电源电压:5 V to 15 V 工作电源电流:133 mA to 400 mA 最大工作温度:+ 70 C |
| TS-MAC-X2-U3 | 功能描述:开发软件 Ethernet MAC TriSPD RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TS-MAC-X2-U4 | 功能描述:开发软件 ETHERNET MAC TRI-SPEED RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TS-MAC-X2-UT4 | 功能描述:开发软件 ETHERNET MAC TRI-SPEED RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TSMACXMU2 | 功能描述:以太网模块 TriSpd Ethernet MAC RoHS:否 制造商:Lantronix 产品:Device Servers 数据速率:300 bps to 921.6 kbps, 10 Mbps, 100 Mbps 接口类型:Ethernet, Serial 工作电源电压:5 V to 15 V 工作电源电流:133 mA to 400 mA 最大工作温度:+ 70 C |
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