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参数资料
| 型号： | TS-MAC-SC-UT4 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 61/66页 |
| 文件大小： | 0K |
| 描述： | SITE LICENSE ETH MAC TRI SC/SCM |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | TSMACSCUT4 |
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Lattice Semiconductor
Support Resources
? TN1196 - LatticeECP3 Marvell 1 GbE (1000BASE-X) Physical/MAC Layer Interoperability
? TN1197 - LatticeECP3/Marvell SGMII Physical/MAC Layer Interoperability
LatticeSCM
? DS1004 , LatticeSC/M Family Data Sheet
? DS1005 , Lattice SC/M Family flexiPCS Data Sheet
Document
IP Core
Date
February 2006
May 2006
July 2006
November 2006
May 2007
August 2007
Version
01.0
01.1
01.2
01.3
01.4
01.5
Version
2.0
2.1
2.2
2.3
2.4
2.4
Change Summary
Initial release.
Added support for LatticeECP2 family.
Added support for LatticeSC family.
Added support for LatticeECP2M family.
Added support for LatticeXP2 family.
Revised Transmit and Receive Control Register Description.
Updated description and diagram for Successful Transmission of a
64-Byte Frame -Tx MAC Application Interface.
September 2007
01.6
2.4
Updated description for Bit 30 in the Receive Statistics Vector
Description table.
September 2007
November 2007
01.7
01.8
2.4
2.4
Updated MAC Address Register mnemonic and POR.
Updated Performance and Resource Utilization table in the
LatticeXP2 appendix.
January 2008
January 2008
January 2008
June 2008
01.9
02.0
02.1
02.2
2.5
2.5
2.5
2.6
Added Software Requirements text section.
Updated the Core Generation and Simulation section.
Updated part numbers listed in appendices. U2 changed to U3.
TSMAC IP core Internal Registers table - Corrected the POR value
for Inter-Packet Gap Register. Value changed to 000CH.
September 2008
02.4
2.7
Expanded Feature list.
Updated General Description text section.
Added Tri-Speed 10/100/1G Ethernet MAC Core Block Diagram
(Gigabit MAC or SGMII Easy Connect options).
Added VLAN-Tagged Ethernet Frame Format diagram.
Added Ethernet Control Pause Frame Format diagram.
Added Tri-Speed 10/100/1G Ethernet MAC Core System Block Dia-
gram (Gigabit MAC option).
Added Tri-Speed 10/100/1G Ethernet MAC Core System Block Dia-
gram (SGMII Easy Connect option).
Updated Signal Descriptions table.
Updated Parameter Descriptions table.
Updated Receiving a PAUSE Frame text section.
Updated Receive Statistics Vector Description table.
Updated Internal Data Buffer and FIFO Interfaces text section.
Updated Internal Registers text section.
Updated MODE (R/W) Register Descriptions table.
Updated Transmit and Receive Control (R/W) Register Descriptions
table.
Added the Core Generation text section.
IPUG51_03.0, December 2010
61
Tri-Speed Ethernet MAC User’s Guide
相关PDF资料 |
PDF描述 |
|---|---|
| VI-J0T-EZ-F4 | CONVERTER MOD DC/DC 6.5V 25W |
| M3CGK-2620K | IDC CABLE - MKC26K/MC26F/MCS26K |
| TS-MAC-PM-UT4 | SITE LICENSE ETH MAC TRI ECP2M |
| VI-J0T-EZ-F2 | CONVERTER MOD DC/DC 6.5V 25W |
| TS-MAC-P2-UT4 | SITE LICENSE ETH MAC TRI ECP2 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSMACX2U2 | 功能描述:以太网模块 TriSpd Ethernet MAC RoHS:否 制造商:Lantronix 产品:Device Servers 数据速率:300 bps to 921.6 kbps, 10 Mbps, 100 Mbps 接口类型:Ethernet, Serial 工作电源电压:5 V to 15 V 工作电源电流:133 mA to 400 mA 最大工作温度:+ 70 C |
| TS-MAC-X2-U3 | 功能描述:开发软件 Ethernet MAC TriSPD RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TS-MAC-X2-U4 | 功能描述:开发软件 ETHERNET MAC TRI-SPEED RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TS-MAC-X2-UT4 | 功能描述:开发软件 ETHERNET MAC TRI-SPEED RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TSMACXMU2 | 功能描述:以太网模块 TriSpd Ethernet MAC RoHS:否 制造商:Lantronix 产品:Device Servers 数据速率:300 bps to 921.6 kbps, 10 Mbps, 100 Mbps 接口类型:Ethernet, Serial 工作电源电压:5 V to 15 V 工作电源电流:133 mA to 400 mA 最大工作温度:+ 70 C |
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