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| 型号： | TS-MAC-SC-UT4 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 63/66页 |
| 文件大小： | 0K |
| 描述： | SITE LICENSE ETH MAC TRI SC/SCM |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | TSMACSCUT4 |
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Appendix A:
Resource Utilization
This appendix gives resource utilization information for Lattice FPGAs using the TSMAC IP core. The IP configura-
tions shown in this chapter were generated using the IPexpress software tool. IPexpress is the Lattice IP configura-
tion utility, and is included as a standard feature of the Diamond and ispLEVER design tools. Details regarding the
usage of IPexpress can be found in the IPexpress and Diamond and ispLEVER help systems. For more information
on the Diamond or ispLEVER design tools, visit the Lattice web site at: www.latticesemi.com/software .
LatticeECP and LatticeEC FPGAs
Table A-1. Performance and Resource Utilization 1
Configuration
Operational
MIIM Module
No
No
Yes
Yes
Option 2
Classic
Gigabit
Classic
Gigabit
SLICEs
1327
1084
1465
1225
LUTs
1844
1437
1992
1564
Registers
1205
1086
1358
1223
EBRs
2
1
2
1
External Pins
25
22
27
24
f MAX (MHz)
125
125
125
125
1. Performance and utilization data are generated targeting an LFEC10E-5F484C device using Lattice Diamond 1.0 and Synplify Pro for Lat-
tice D-2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed
grade within the LatticeECP/EC family.
2. The SGMII Easy Connect option is only available on device families with SERDES I/O.
Ordering Part Number
The Ordering Part Number (OPN) for the Tri-Speed Ethernet Media Access Controller IP core targeting ?
LatticeECP/EC devices is TS-MAC-E2-U4.
LatticeECP2 FPGAs
Table A-2. Performance and Resource Utilization 1
Configuration
Operational
MIIM Module
No
No
Yes
Yes
Option 2
Classic
Gigabit
Classic
Gigabit
SLICEs
1337
1086
1494
1243
LUTs
1855
1450
2031
1620
Registers
1197
1061
1352
1213
EBRs
2
1
2
1
External Pins
25
22
27
24
f MAX (MHz)
125
125
125
125
1. Performance and utilization data are generated targeting an LFE2-50E-6F672C device using Lattice Diamond 1.0 and Synplify Pro for Lat-
tice D-2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed
grade within the LatticeECP2 family.
2. The SGMII Easy Connect option is only available on device families with SERDES I/O.
Ordering Part Number
The Ordering Part Number (OPN) for the Tri-Speed Ethernet Media Access Controller IP core targeting
LatticeECP2 devices is TS-MAC-P2-U4.
IPUG51_03.0, December 2010
63
Tri-Speed Ethernet MAC User’s Guide
相关PDF资料 |
PDF描述 |
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| VI-J0T-EZ-F4 | CONVERTER MOD DC/DC 6.5V 25W |
| M3CGK-2620K | IDC CABLE - MKC26K/MC26F/MCS26K |
| TS-MAC-PM-UT4 | SITE LICENSE ETH MAC TRI ECP2M |
| VI-J0T-EZ-F2 | CONVERTER MOD DC/DC 6.5V 25W |
| TS-MAC-P2-UT4 | SITE LICENSE ETH MAC TRI ECP2 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSMACX2U2 | 功能描述:以太网模块 TriSpd Ethernet MAC RoHS:否 制造商:Lantronix 产品:Device Servers 数据速率:300 bps to 921.6 kbps, 10 Mbps, 100 Mbps 接口类型:Ethernet, Serial 工作电源电压:5 V to 15 V 工作电源电流:133 mA to 400 mA 最大工作温度:+ 70 C |
| TS-MAC-X2-U3 | 功能描述:开发软件 Ethernet MAC TriSPD RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TS-MAC-X2-U4 | 功能描述:开发软件 ETHERNET MAC TRI-SPEED RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TS-MAC-X2-UT4 | 功能描述:开发软件 ETHERNET MAC TRI-SPEED RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TSMACXMU2 | 功能描述:以太网模块 TriSpd Ethernet MAC RoHS:否 制造商:Lantronix 产品:Device Servers 数据速率:300 bps to 921.6 kbps, 10 Mbps, 100 Mbps 接口类型:Ethernet, Serial 工作电源电压:5 V to 15 V 工作电源电流:133 mA to 400 mA 最大工作温度:+ 70 C |
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