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| 型号： | TS-MAC-SC-UT4 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 29/66页 |
| 文件大小： | 0K |
| 描述： | SITE LICENSE ETH MAC TRI SC/SCM |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | TSMACSCUT4 |
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Lattice Semiconductor
Functional Description
GMII Management Register Access Control (R/W)
Mnemonic: GMII_MNG_CTL
POR Value = 0000H.
The GMII Management Access register controls the Management Interface Module. This register can be overwrit-
ten only when the interface is not busy. A write operation will be ignored when the interface is busy.
Name
Rsvd
Cmd_fin
RW_phyreg
Phy_add
Rsvd
Reg_add
Range
15
14
13
12:8
7:5
4:0
Description
Reserved .
Command Finished . When high, it means the interface has completed the intended oper-
ation. This bit is set to 0 when the interface is busy.
Read/Write PHY Registers
? When ‘1’ -> write operation
? When ‘0’ -> read operation
GMII PHY Address . The address of the accessed PHY Bit 12 is the most significant bit,
and it is the first PHY address bit to be transmitted and received.
Reserved .
GMII Register Address . The address of the register accessed. Bit 4 is the most significant
bit and is the first register address bit to be transmitted or received.
GMII Management Access Data (R/W)
Mnemonic: GMII_MNG_DAT
POR Value = 0000H.
The contents of this register will be transmitted when a write operation is to be performed. When a read operation
is performed, this register will contain the value that was read from a PHY register. This register should be read
only after the cmd_fin bit in the control register is set.
Name
GMII_dat
Range
15:0
Description
GMII Data . Bit 15 is the most significant bit, corresponding to bit 15 of the accessed regis-
ter.
Multicast Tables (R/W), Set of Eight
Mnemonic: MLT_TAB_[0-7]
POR Value = 0000H.
When the core is programmed to receive multicast frames, a filtering scheme is used to decide whether the frame
should be received or not. The six middle bits of the most significant byte of the CRC value, calculated for the des-
tination address, are used as a key to the 64-bit hash table. The three most significant bits select one of the eight
tables, and the three least significant bits select a bit. The frame is received only if this bit is set.
Name
Multicast_table_[0-7]
Range
7:0
Description
Multicast Table . Eight tables that make a 64-bit hash.
IPUG51_03.0, December 2010
29
Tri-Speed Ethernet MAC User’s Guide
相关PDF资料 |
PDF描述 |
|---|---|
| VI-J0T-EZ-F4 | CONVERTER MOD DC/DC 6.5V 25W |
| M3CGK-2620K | IDC CABLE - MKC26K/MC26F/MCS26K |
| TS-MAC-PM-UT4 | SITE LICENSE ETH MAC TRI ECP2M |
| VI-J0T-EZ-F2 | CONVERTER MOD DC/DC 6.5V 25W |
| TS-MAC-P2-UT4 | SITE LICENSE ETH MAC TRI ECP2 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSMACX2U2 | 功能描述:以太网模块 TriSpd Ethernet MAC RoHS:否 制造商:Lantronix 产品:Device Servers 数据速率:300 bps to 921.6 kbps, 10 Mbps, 100 Mbps 接口类型:Ethernet, Serial 工作电源电压:5 V to 15 V 工作电源电流:133 mA to 400 mA 最大工作温度:+ 70 C |
| TS-MAC-X2-U3 | 功能描述:开发软件 Ethernet MAC TriSPD RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TS-MAC-X2-U4 | 功能描述:开发软件 ETHERNET MAC TRI-SPEED RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TS-MAC-X2-UT4 | 功能描述:开发软件 ETHERNET MAC TRI-SPEED RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TSMACXMU2 | 功能描述:以太网模块 TriSpd Ethernet MAC RoHS:否 制造商:Lantronix 产品:Device Servers 数据速率:300 bps to 921.6 kbps, 10 Mbps, 100 Mbps 接口类型:Ethernet, Serial 工作电源电压:5 V to 15 V 工作电源电流:133 mA to 400 mA 最大工作温度:+ 70 C |
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