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参数资料
| 型号： | TS-MAC-SC-UT4 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 53/66页 |
| 文件大小： | 0K |
| 描述： | SITE LICENSE ETH MAC TRI SC/SCM |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | TSMACSCUT4 |
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Lattice Semiconductor
MAC Control Register (R/W)
Mnemonic: MACCNTL
POR Value = 00H
Application Support
Name
Rsvd [7:5]
ignore next packet
tx_fifo_empty
rx_fifo full
fifo control frame
send pause request
Range
7-5
4
3
2
1
0
Description
Reserved
ignore next packet : This bit asserts the ignore_next_pkt pin on the TSMAC
IP core. See Table 2-1 on page 14 for more information.
tx_fifo_empty : This bit gets ORed with the FIFO empty signal. The ORed
this bit you can mimic the Tx FIFO being empty. Also note that the applica-
tion design only has one loopback FIFO. So the Tx FIFO is the same as the
Rx FIFO.
rx_fifo full : This bit gets ORed with the FIFO full signal. The ORed output
sets the rx_fifo_full pin on the TSMAC IP core. See Table 2-1 on page 14 for
more information on this TSMAC IP core signal. Note by setting this bit you
can mimic the rx fifo being full. Also note that the application design only has
one loopback FIFO. So the Tx FIFO is the same as the Rx FIFO.
fifo control frame : This bit sets the tx_fifoctrl pin on the TSMAC IP core.
See Table 2-1 on page 14 for more information on this TSMAC IP core sig-
nal.
send pause request : This bit gets ORed with the Tx FIFO almost full signal.
The ORed output sets the tx_sndpausreq pin on the TSMAC IP core. See
When this bit is set High OR the FIFO is almost full tx_sndpausreq is
asserted, otherwise tx_sndpausreq is de-asserted.
Pause Timer Register - Low Byte (R/W)
Mnemonic: PAUSTMRL
POR Value = 00H
Name
pause timer Low bits
[7:0]
Range
7:0
Description
Pause Timer Low bits : These reg bits set the tx_sndpaustim[7:0] pins on
the TSMAC IP core. See Table 2-1 on page 14 for more information on this
TSMAC IP core signal.
Pause Timer Register - High Byte (R/W)
Mnemonic: PAUSTMRH
POR Value = 00H
Name
pause timer High bits
[7:0]
Range
7:0
Description
Pause Timer High bits : These bits set the tx_sndpaustim[15:8] pins on the
TSMAC IP core. See Table 2-1 on page 14 for more information on this
TSMAC IP core signal.
IPUG51_03.0, December 2010
53
Tri-Speed Ethernet MAC User’s Guide
相关PDF资料 |
PDF描述 |
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| VI-J0T-EZ-F4 | CONVERTER MOD DC/DC 6.5V 25W |
| M3CGK-2620K | IDC CABLE - MKC26K/MC26F/MCS26K |
| TS-MAC-PM-UT4 | SITE LICENSE ETH MAC TRI ECP2M |
| VI-J0T-EZ-F2 | CONVERTER MOD DC/DC 6.5V 25W |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TSMACX2U2 | 功能描述:以太网模块 TriSpd Ethernet MAC RoHS:否 制造商:Lantronix 产品:Device Servers 数据速率:300 bps to 921.6 kbps, 10 Mbps, 100 Mbps 接口类型:Ethernet, Serial 工作电源电压:5 V to 15 V 工作电源电流:133 mA to 400 mA 最大工作温度:+ 70 C |
| TS-MAC-X2-U3 | 功能描述:开发软件 Ethernet MAC TriSPD RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TS-MAC-X2-U4 | 功能描述:开发软件 ETHERNET MAC TRI-SPEED RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TS-MAC-X2-UT4 | 功能描述:开发软件 ETHERNET MAC TRI-SPEED RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TSMACXMU2 | 功能描述:以太网模块 TriSpd Ethernet MAC RoHS:否 制造商:Lantronix 产品:Device Servers 数据速率:300 bps to 921.6 kbps, 10 Mbps, 100 Mbps 接口类型:Ethernet, Serial 工作电源电压:5 V to 15 V 工作电源电流:133 mA to 400 mA 最大工作温度:+ 70 C |
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