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| 型号： | TS-MAC-SC-UT4 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 27/66页 |
| 文件大小： | 0K |
| 描述： | SITE LICENSE ETH MAC TRI SC/SCM |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | TSMACSCUT4 |
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Lattice Semiconductor
Functional Description
Transmit and Receive Control (R/W)
Mnemonic: TX_RX_CTL
POR Value = 0000H
This register can be overwritten only when the Rx MAC and the Tx MAC are disabled. This register controls the
various features of the MAC.
Name
Rsvd
Receive_short
Receive_brdcst
Drop_control
Hden
Receive_mltcst
Receive_pause
Tx_dis_fcs
Discard_fcs
Prms
Range
15:9
8
7
6
5
4
3
2
1
0
Description
Reserved .
Receive Short Frames . When high, enables the Rx MAC to receive frames shorter than
64 bytes.
Receive Broadcast . When high, enables the Rx MAC to receive broadcast frames
Drop control . When high, received pause control frames are dropped internal to the MAC
and not transferred to the external Rx client FIFO.
Half-duplex Enable (10/100 mode only). When high, configures the Tx MAC to operate in
half-duplex mode.
Receive Multicast . When high, the multicast frames will be received per the filtering rules
for such frames. When low, no Multicast (except PAUSE) frames will be received.
Receive PAUSE . When set, the Rx MAC will indicate the Rx PAUSE frame reception to
the Tx MAC and thereby cause the Tx MAC to pause sending data frames for the period
specified within the Rx PAUSE frame. Note this indication is independent of the
Drop_control bit setting.
Transmit Disable FCS . When set, the FCS field generation is disabled in the Tx MAC.
Rx Discard FCS and Pad . When set, the FCS and any of the padding bytes of an IEEE
802.3 frame are stripped off the frame before it is transferred to the Rx FIFO. When low,
the entire frame is transferred into the Rx FIFO. Note: Discarding padding bytes is only
applicable to pure IEEE 802.3 frames (such as in backplane applications) and will not
function on Ethernet frames (IP, UDP, ICMP, etc.) where the length field is now interpreted
as a protocol type field.
Promiscuous Mode . When asserted, all filtering schemes are abandoned and the Rx
MAC receives frames with any address.
Maximum Packet Size (R/W)
Mnemonic: MAX_PKT_SIZE
POR Value = 05EEH (1518 decimal)
This register can be overwritten only when the MAC is disabled. All frames longer than the value (number of bytes)
in this register will be tagged as long frames.
Name
Max_frame
Range
15:0
Description
Maximum size of the packet than can be handled by the core.
IPG (Inter-Packet Gap) (R/W)
Mnemonic: IPG_VAL
POR Value = 000CH
Rsvd
IPG
Name
Range
15:5
4:0
Description
Reserved.
Inter-packet gap value in units of (byte time).
IPUG51_03.0, December 2010
27
Tri-Speed Ethernet MAC User’s Guide
相关PDF资料 |
PDF描述 |
|---|---|
| VI-J0T-EZ-F4 | CONVERTER MOD DC/DC 6.5V 25W |
| M3CGK-2620K | IDC CABLE - MKC26K/MC26F/MCS26K |
| TS-MAC-PM-UT4 | SITE LICENSE ETH MAC TRI ECP2M |
| VI-J0T-EZ-F2 | CONVERTER MOD DC/DC 6.5V 25W |
| TS-MAC-P2-UT4 | SITE LICENSE ETH MAC TRI ECP2 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TSMACX2U2 | 功能描述:以太网模块 TriSpd Ethernet MAC RoHS:否 制造商:Lantronix 产品:Device Servers 数据速率:300 bps to 921.6 kbps, 10 Mbps, 100 Mbps 接口类型:Ethernet, Serial 工作电源电压:5 V to 15 V 工作电源电流:133 mA to 400 mA 最大工作温度:+ 70 C |
| TS-MAC-X2-U3 | 功能描述:开发软件 Ethernet MAC TriSPD RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TS-MAC-X2-U4 | 功能描述:开发软件 ETHERNET MAC TRI-SPEED RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TS-MAC-X2-UT4 | 功能描述:开发软件 ETHERNET MAC TRI-SPEED RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| TSMACXMU2 | 功能描述:以太网模块 TriSpd Ethernet MAC RoHS:否 制造商:Lantronix 产品:Device Servers 数据速率:300 bps to 921.6 kbps, 10 Mbps, 100 Mbps 接口类型:Ethernet, Serial 工作电源电压:5 V to 15 V 工作电源电流:133 mA to 400 mA 最大工作温度:+ 70 C |
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