- 您现在的位置：买卖IC网 > PDF目录297706 > V58C2256324SAH-40 (PROMOS TECHNOLOGIES INC) 8M X 32 DDR DRAM, 0.6 ns, PBGA144 PDF资料下载
参数资料
| 型号： | V58C2256324SAH-40 |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM, 0.6 ns, PBGA144 |
| 封装： | LEAD FREE, BGA-144 |
| 文件页数： | 1/37页 |
| 文件大小： | 557K |
| 代理商： | V58C2256324SAH-40 |
当前第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页
1
V58C2256324SA
HIGH PERFORMANCE LOW POWER
2.5 VOLT 8M X 32 DDR SDRAM
4 BANKS X 2M X 32
V58C2256324SA Rev. 1.0 November 2003
28
33
36
40
System Frequency (fCK)
350 MHz
300 MHz
275 MHz
250MHz
Clock Cycle Time (tCK3)4.0
4.0
4.5
5.0
Clock Cycle Time (tCK4)3.3
3.3
3.6
4.0
Clock Cycle Time (tCK5)
2.85
3.3
3.6
4.0
Features
■ 4 banks x 2M x 32 organization
■ High speed data transfer rates with system frequency
up to 350 MHz
■ Data Mask for Write Control (DM)
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency: 3, 4, 5
■ Programmable Wrap Sequence: Sequential
or Interleave
■ Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
■ Automatic and Controlled Precharge Command
■ Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 4096 cycles/32ms
■ Available in 144-ball BGA
■ Double Data Rate (DDR)
■ Bidirectional Data Strobe (DQs) for input and output
data, active on both edges
■ On-Chip DLL aligns DQ and DQs transitions with CLK
transitions
■ Differential clock inputs CLK and /CLK
■ Power Supply 2.5V ± 0.2V
■ 2.5V SSTL2 Weak Mode interface(Z0=34 ohm)
■ 1.8V Matched Impedance Interface (Z0=60 ohm)
Description
The V58C2256324SA is a four bank DDR DRAM
organized as 4 banks x 2M x 32. The V58C2256324SA
achieves high speed data transfer rates by employing a
chip architecture that prefetches multiple bits and then
synchronizes the output data to a system clock
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
transactions are possible on both edges of DQS.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device
.
Device Usage Chart
Operating
Temperature
Range
Package Outline
CLK Cycle Time (ns)
Power
Temperature
Mark
144-ball BGA
-28
-33
-36
-40
Std.
L
0°C to 70°C
Blank
相关PDF资料 |
PDF描述 |
|---|---|
| V59C1512404QBLF3I | 128M X 4 DDR DRAM, 0.45 ns, PBGA60 |
| V5A010CB3H | SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 0.6A, 125VDC, 4.4mm, PANEL MOUNT |
| V5B010FB3 | SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 2.3mm, PANEL MOUNT |
| V5B030CB3H | SNAP ACTING/LIMIT SWITCH, SPST, MOMENTARY, 0.6A, 125VDC, 4.4mm, PANEL MOUNT |
| V5B110SB | SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 2.4mm, PANEL MOUNT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| V58C2256404S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM |
| V58C2256804S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM |
| V58C2256804SAT-5 | 制造商:Mosel Vitelic Corporation 功能描述:SDRAM, DDR, 32M x 8, 66 Pin, Plastic, TSSOP |
| V58C265164S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:64 Mbit DDR SDRAM 2.5 VOLT 4M X 16 |
| V58C265404S | 制造商:MOSEL 制造商全称:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 16M X 4 DDR SDRAM 4 BANKS X 4Mbit X 4 |
发布紧急采购，3分钟左右您将得到回复。