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| 型号： | V58C2256324SAH-40 |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM, 0.6 ns, PBGA144 |
| 封装： | LEAD FREE, BGA-144 |
| 文件页数： | 36/37页 |
| 文件大小： | 557K |
| 代理商： | V58C2256324SAH-40 |
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V58C2256324SA Rev. 1.0 November 2003
ProMOS TECHNOLOGIES
V58C2256324SA
DataStrobeandDataMask
OperationatBurstReads
TheDataStrobesprovidea3-stateoutputsignaltothereceivercircuitsofthecontrollerduringareadburst.Thedatastrobesignalgoes
1clockcyclelowbeforedataisdrivenbytheDDRSDRAMandthentoggleslowtohighandhightolowtilltheendoftheburst.The
CASlatencyisspecifiedtothefirstlowtohightransition.TheedgesoftheOutputDatasignalsandtheedgesofthedatastrobesignals
duringareadarenominallycoincidentwithedgesoftheinputclock.ThetoleranceoftheseedgesisspecifiedbytheparameterstAC
andtDQSCKandisreferencedtothecrossingpointoftheCLKand/CLKsignal.ThetDQSQtimingparameterdescribestheskew
betweenthedatastrobeedgeandtheoutputdataedge.
ThefollowingtablesummarizesthemappingofDQSxandDMxsignalstothedatabus.
MappingofDQSxandDMx
Theminimumtimeduringwhichtheoutputdataisvalidiscriticalforthereceivingdevice.ThisalsoappliestotheDataStrobeDQS
duringareadsinceitistightlycoupledtotheoutputdata.TheparameterstQHandtDQSQdefinetheminimumoutputdatavalidwindow.
Priortoaburstofreaddata,giventhatthedeviceisnotcurrentlyinburstreadmode,thedatastrobesignalstransitfromHi-Ztoavalid
logiclow.ThisisreferredtoasthedatastrobeìreadpreambletRPRE.Thistransitionhappensoneclockpriortothefirstedgeofvalid
data.
Oncetheburstofreaddataisconcluded,giventhatnosubsequentburstreadoperationisinitiated,thedatastrobesignalstransitfrom
avalidlogiclowtoHi-Z.ThisisreferredtoasthedatastrobeìreadpostambletRPST.
DQSTimingforRead
datastrobesignal
datamasksignal
Controlleddatabus
DQS0
DM0
DQ7..DQ0
DQS1
DM1
DQ8..DQ15
DQS2
DM2
DQ16..DQ23
DQS3
DM3
DQ24..DQ31
DQx
CLK,
/CLK
DQS
"Preamble"
"Postamble"
VIH
VTT
VIL
t
RPRE
t
RPST
D
D+1
D+2
D+3
VIH
VTT
VIL
t
DQSQ
t
AC
T0
T1
T2
T3
T4
VIH
VIL
t
CH
t
CL
t
CK
t
DQSCK
t
HP
t
QH
t
QHS
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