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参数资料
| 型号： | V58C2256324SAH-40 |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM, 0.6 ns, PBGA144 |
| 封装： | LEAD FREE, BGA-144 |
| 文件页数： | 35/37页 |
| 文件大小： | 557K |
| 代理商： | V58C2256324SAH-40 |
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V58C2256324SA Rev. 1.0 November 2003
ProMOS TECHNOLOGIES
V58C2256324SA
SignalandTimingDescription
GeneralDescription
The256MbitDDRSDRAMisa32MByteSynchronousDDRSDRAM. Itconsistsoffourbanks.Eachbankisorganizedas4096rows
x512columnsx32bits.
ReadandWriteaccessesareburstoriented.AccessesbeginwiththeregistrationofanActivatecommand,whichisthenfollowedbya
ReadorWritecommand.TheaddressbitsregisteredcoincidentwiththeActivatecommandareusedtoselectthebankandtherowto
beaccessed.BA1andBA0selectthebank,addressbitsA11..A0selecttherow.AddressbitsA9,A7... A0registeredcoincident
withthe ReadorWritecommandareusedtoselectthestartingcolumnlocationfortheburstaccess.
TheregularSingleDataRateSDRAMreadandwritecyclesonlyusetherisingedgeoftheexternalclockinput.FortheDDRSDRAM,
thespecialsignalsDQSx(DataStrobe)areusedtomarkthedatavalidwindow.Duringreadbursts,thedatavalidwindowcoincides
withthehighorlowleveloftheDQSxsignals.Duringwritebursts,theDQSxsignalmarksthecenterofthevaliddatawindow.Datais
availableateveryrisingandfallingedgeofDQSx,thereforethedatatransferrateisdoubled.
ForReadaccesses,theDQSxsignalsarealignedtotheclocksignalCLK.
SpecialSignalDescription
ClockSignal
TheDDRSDRAMoperateswithadifferentialclock(CLKand/CLK )input.CLKisusedtolatchtheaddressandcommandsignals.Data
inputandDMxsignalsarelatchedwithDQSx.TheDDRSDRAMimplementsaDelayLockedLoopcircuit(DLL)whichtracksbothedges
oftheCLKinputsignalandalignstheDQSoutputedgeswiththeCLKinputedges.
TheminimumandmaximumclockcycletimeisdefinedbytCK.ThemaximumvaluefortCKisdefinedtoprovidealowerboundforthe
operationfrequencyoftheinternalDLLcircuit.Theminimumandmaximumclockdutycyclearespecifiedusingtheminimumclockhigh
timetCHandtheminimumclocklowtimetCLrespectively.
TheinternalDLLcircuitrequiresadditional200clockcyclesafterDLLresetforinternalclockstabilization.
CommandInputsandAddresses
LikesingledatarateSDRAMs,eachcombinationofRAS#,CAS#andWE#inputinconjunctionwithCS#inputatarisingedgeofthe
clockdeterminesaDDRSDRAMcommand.
CommandandAddressSignalTiming
Valid
CLK,/CLK
Address,
CS#,RAS#,
CAS#,WE#,
CKE
VIH
VTT
VIL
VIH
VIL
t
IS
t
IH
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