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参数资料
| 型号： | V58C2256324SAH-40 |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 8M X 32 DDR DRAM, 0.6 ns, PBGA144 |
| 封装： | LEAD FREE, BGA-144 |
| 文件页数： | 26/37页 |
| 文件大小： | 557K |
| 代理商： | V58C2256324SAH-40 |
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32
V58C2256324SA Rev. 1.0 November 2003
ProMOS TECHNOLOGIES
V58C2256324SA
Power & DC Operating Conditions (SSTL_2 In/Out)
Recommended operating conditions (Voltage referenced to VSS=0V, TA=0 to 65°C)
AC Input Operating Conditions
Recommended operating conditions
(Voltage referenced to VSS=0V, VDD=2.5V+ 5%, VDDQ=2.5V+ 5%, TA=0 to 65°C)
SSTL_2 AC Test Conditions
Notes: 1. Input waveform timing is referenced to the input signal crossing the VREF level applied to the device.
2. Compliant devices must still meet the VIH (AC) and VIL (AC) specifications under actual use conditions.
3. The 1 V/ns input signal minimum slew rate is to be maintained in the VIL max (AC) to VIL min (AC) range of the input
signal swing.
Parameter
Symbol
Min
Typ
Max
Unit
Device Supply voltage
VDD
2.38
2.50
2.63
V
Output Supply voltage
VDDQ
2.38
2.50
2.63
V
Reference voltage
VREF
0.49*VDDQ
-
0.51*VDDQ
V
Termination voltage
Vtt
VREF-0.04
VREF
VREF+0.04
V
Input logic high voltage
VIH
VREF+0.35
-
VDDQ+0.30
V
Input logic low voltage
VIL
VSSQ-0.30
-
VREF-0.15
V
Output Levels: Matched Impedance Mode
1.8V
High Current at VOUT=VDDQ-0.373V
Low Current at VOUT=0.373V
IOH
-5
-
mA
IOL
5-
-
mA
Output Levels: SSTL2 Weak Mode 2.5V
High Current at VOUT=VDDQ-0.373V
Low Current at VOUT=0.373V
IOH
-9
-
mA
IOL
9-
-
mA
Parameter
Symbol
Min
Typ
Max
Unit
Input High (Logic 1) Voltage; DQ
VIH
VREF+0.35
-
V
Input Low (Logic 0) Voltage; DQ
VIL
-
VREF-0.35
V
Clock Input Differential Voltage; CK and CK
VID
0.7
-
VDDQ+0.6
V
Clock Input Crossing Point Voltage; CK and CK
VIX
0.5*VDDQ-0.2
-
0.5*VDDQ+0.2
V
Symbol
Parameter
Value
Units
Notes
VREF
Input Reference Voltage
0.5*VDDQ
V1
VSWING (max)
Input Signal Maximum Peak to Peak Swing
1.5
V
1, 2
SLEW
Input Signal Minimum Slew Rate
1.0
V/ns
3
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