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参数资料
| 型号： | W949D2CBJX5E |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 16M X 32 DDR DRAM, 5 ns, PBGA90 |
| 封装： | 8 X 13 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-90 |
| 文件页数： | 35/60页 |
| 文件大小： | 1160K |
| 代理商： | W949D2CBJX5E |
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W949D6CB / W949D2CB
512Mb Mobile LPDDR
Publication Release Date: Jun, 14, 2011
- 40 -
Revision A01-006
7.7.1 Precharge Command
= Don't Care
(High)
CK
CKE
CS
RAS
CAS
WE
Address
BA=BANK Address
(if A10 = L,otherwise Don't Care)
BA
BA0,BA1
A10
All Banks
One Bank
7.8 Auto Precharge
Auto Precharge is a feature which performs the same individual bank precharge function as described above, but
without requiring an explicit command. This is accomplished by using A10 (A10 = High), to enable Auto Precharge in
conjunction with a specific READ or WRITE command. A precharge of the bank / row that is addressed with the
READ or WRITE command is automatically performed upon completion of the read or write burst. Auto Precharge is
non persistent in that it is either enabled or disabled for each individual READ or WRITE command.
Auto Precharge ensures that a precharge is initiated at the earliest valid stage within a burst. The user must not
issue another command to the same bank until the precharing time (tRP) is completed. This is determined as if an
explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the
Operation section of this specification.
7.9 Refresh Requirements
LPDDR SDRAM devices require a refresh of all rows in any rolling 64ms interval. Each refresh is generated in one of
two ways: by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode.
Dividing the number of device rows into the rolling 64ms interval defines the average refresh interval (tREFI), which is
a guideline to controllers for distributed refresh timing.
7.10 Auto Refresh
AUTO REFRESH command is used during normal operation of the LPDDR SDRAM. This command is non
persistent, so it must be issued each time a refresh is required.
The refresh addressing is generated by the internal refresh controller. The LPDDR SDRAM requires AUTO
REFRESH commands at an average periodic interval of tREFI.
相关PDF资料 |
PDF描述 |
|---|---|
| WF128K32N-150HC5 | 512K X 8 FLASH 5V PROM MODULE, 150 ns, HIP66 |
| WPS512K8LB-85GM | 512K X 8 STANDARD SRAM, 85 ns, PDSO32 |
| WPS128K32GV-17PJI | 512K X 8 MULTI DEVICE SRAM MODULE, 17 ns, PQMA68 |
| WF2M32B-150HM5 | 8M X 8 FLASH 5V PROM MODULE, 150 ns, CHIP66 |
| WF2M32B-120G2UC5 | 8M X 8 FLASH 5V PROM MODULE, 120 ns, CQFP68 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W949D2CBJX5ETR | 制造商:Winbond Electronics Corp 功能描述:512M MDDR, X32, 200MHZ |
| W949D2CBJX5I | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip Mobile LPDDR SDRAM 512M-Bit 16Mx32 1.8V 90-Pin VFBGA |
| W949D2CBJX5I TR | 制造商:Winbond Electronics Corp 功能描述:512M MDDR, X32, 200MHZ, INDUST |
| W949D2CBJX6E | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip Mobile LPDDR SDRAM 512M-Bit 16Mx32 1.8V 90-Pin VFBGA |
| W949D2CBJX6ETR | 制造商:Winbond Electronics Corp 功能描述:512M MDDR, X32, 166MHZ, 65NM |
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