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参数资料
| 型号： | W949D2CBJX5E |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 16M X 32 DDR DRAM, 5 ns, PBGA90 |
| 封装： | 8 X 13 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-90 |
| 文件页数： | 43/60页 |
| 文件大小： | 1160K |
| 代理商： | W949D2CBJX5E |
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W949D6CB / W949D2CB
512Mb Mobile LPDDR
Publication Release Date: Jun, 14, 2011
- 48 -
Revision A01-006
8.4 IDD Specification Parameters and Test Conditions
8.4.1 IDD Specification Parameters and Test Conditions
[Recommended Operating Conditions; Notes 1-4]
(512Mb, X16)
PARAMETER
SYMBOL
TEST CONDITION
- 5
- 6
- 75
UNIT
Operating one
bank active-
precharge
current
IDD0
tRC = tRCmin ; tCK = tCKmin ; CKE is HIGH;
CS is HIGH between valid
commands; address inputs are SWITCHING; data bus inputs are
STABLE
40
38
35
mA
Precharge
power-down
standby current
IDD2P
all banks idle, CKE is LOW;
CS is HIGH, tCK = tCKmin ;
address and control inputs are SWITCHING; data bus inputs
are STABLE
Low
power
0.6
mA
Normal
power
0.8
Precharge
power-down
standby current
with clock stop
IDD2PS
all banks idle, CKE is LOW;
CS is HIGH, CK = LOW,
=
HIGH; address and control inputs are SWITCHING; data bus
inputs are STABLE
Low
power
0.6
mA
Normal
power
0.8
Precharge non
power-down
standby current
IDD2N
all banks idle, CKE is HIGH;
CS is HIGH, tCK = tCKmin; address and
control inputs are SWITCHING; data bus inputs are STABLE
10
mA
Precharge non
power-down
standby current
with clock stop
IDD2NS
all banks idle, CKE is HIGH;
CS is HIGH, CK = LOW,
= HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
3
mA
Active power-
down standby
current
IDD3P
one bank active, CKE is LOW;
CS is HIGH, tCK = tCKmin;address and
control inputs are SWITCHING; data bus inputs are STABLE
2
mA
Active power-
down standby
current with
clock stop
IDD3PS
one bank active, CKE is LOW;
CS is HIGH, CK = LOW,
= HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
2
mA
Active non
power-down
standby current
IDD3N
one bank active, CKE is HIGH;
CS is HIGH, tCK = tCKmin; address
and control inputs are SWITCHING; data bus inputs are STABLE
15
mA
Active non
power-down
standby current
with clock stop
IDD3NS
one bank active, CKE is HIGH;
CS is HIGH, CK = LOW,
= HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
8
mA
Operating burst
read current
IDD4R
one bank active; BL = 4; CL = 3; tCK = tCKmin ; continuous read bursts;
IOUT = 0 mA; address inputs are SWITCHING; 50% data change each
burst transfer
75
70
mA
Operating burst
write current
IDD4W
one bank active; BL = 4; t CK = t CKmin ; continuous write
bursts; address inputs are SWITCHING; 50% data change each burst
transfer
55
50
mA
Auto-Refresh
Current
IDD5
tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is HIGH; address and
control inputs are SWITCHING; data bus inputs are STABLE
75
mA
Deep Power-
Down current
IDD8(4)
Address and control inputs are STABLE; data bus inputs are STABLE
10
uA
CK
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相关代理商/技术参数 |
参数描述 |
|---|---|
| W949D2CBJX5ETR | 制造商:Winbond Electronics Corp 功能描述:512M MDDR, X32, 200MHZ |
| W949D2CBJX5I | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip Mobile LPDDR SDRAM 512M-Bit 16Mx32 1.8V 90-Pin VFBGA |
| W949D2CBJX5I TR | 制造商:Winbond Electronics Corp 功能描述:512M MDDR, X32, 200MHZ, INDUST |
| W949D2CBJX6E | 制造商:Winbond Electronics Corp 功能描述:DRAM Chip Mobile LPDDR SDRAM 512M-Bit 16Mx32 1.8V 90-Pin VFBGA |
| W949D2CBJX6ETR | 制造商:Winbond Electronics Corp 功能描述:512M MDDR, X32, 166MHZ, 65NM |
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