参数资料
型号: W949D2CBJX5E
厂商: WINBOND ELECTRONICS CORP
元件分类: DRAM
英文描述: 16M X 32 DDR DRAM, 5 ns, PBGA90
封装: 8 X 13 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-90
文件页数: 47/60页
文件大小: 1160K
代理商: W949D2CBJX5E
W949D6CB / W949D2CB
512Mb Mobile LPDDR
Publication Release Date: Jun, 14, 2011
- 51 -
Revision A01-006
8.5 AC Timings
[Recommended Operating Conditions: Notes 1-9]
PARAMETER
SYMBOL
- 5
- 6
- 75
UNIT
NOTES
MIN
MAX
MIN
MAX
MIN
MAX
DQ output access time
from CK/
CK
CL=3
tAC
2.0
5.0
2.0
5.0
2.0
6.0
ns
CL=2
2.0
6.5
2.0
6.5
2.0
6.5
DQS output access time from CK/
CK
CL=3
tDQSCK
2.0
5.0
2.0
5.0
2.0
6.0
ns
CL=2
2.0
6.5
2.0
6.5
2.0
6.5
Clock high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock half period
tHP
Min
(tCL, tCH)
Min
(tCL, tCH)
Min
(tCL, tCH)
ns
10,11
Clock cycle time
CL=3
tCK
5
6
7.5
ns
12
CL=2
12
ns
12
DQ and DM input setup
time
fast
tDS
0.48
0.6
0.8
ns
13,14,15
slow
0.58
0.7
0.9
ns
13,14,16
DQ and DM input hold time
fast
tDH
0.48
0.6
0.8
ns
13,14,15
slow
0.58
0.7
0.9
ns
13,14,16
DQ and DM input pulse width
tDIPW
1.6
1.8
ns
17
Address and control input
setup time
fast
tIS
0.9
1.1
1.3
ns
15,18
slow
1.1
1.3
1.5
ns
16,18
Address and control input
hold time
fast
tIH
0.9
1.1
1.3
ns
15,18
slow
1.1
1.3
1.5
ns
16,18
Address and control input pulse width
tIPW
2.3
2.6
ns
17
DQ & DQS low-impedance time from
CK/
CK
tLZ
1.0
ns
19
DQ & DQS high-impedance
time from CK/
CK
CL=3
tHZ
5.0
6.0
ns
19
CL=2
6.5
DQS-DQ skew
tDQSQ
0.4
0.5
0.6
ns
20
DQ/DQS output hold time from DQS
tQH
tHP-tQHS
ns
11
Data hold skew factor
tQHS
0.5
065
0.75
ns
11
Write command to 1st DQS latching
transition
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS input high-level width
tDQSH
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS input low-level width
tDQSL
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS falling edge to CK setup time
tDSS
0.2
tCK
DQS falling edge hold time from CK
tDSH
0.2
tCK
MODE REGISTER SET command
tMRD
2
tCK
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