- 您现在的位置：买卖IC网 > PDF目录68559 > W949D2CBJX6G (WINBOND ELECTRONICS CORP) 16M X 32 DDR DRAM, 5 ns, PBGA90 PDF资料下载
参数资料
| 型号： | W949D2CBJX6G |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 16M X 32 DDR DRAM, 5 ns, PBGA90 |
| 封装： | 8 X 13 MM, 0.80 MM PITCH, HALOGEN FREE AND LEAD FREE, VFBGA-90 |
| 文件页数： | 40/60页 |
| 文件大小： | 1160K |
| 代理商： | W949D2CBJX6G |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页当前第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页
W949D6CB / W949D2CB
512Mb Mobile LPDDR
Publication Release Date: Jun, 14, 2011
- 45 -
Revision A01-006
7.14 Clock Stop
Stopping a clock during idle periods is an effective method of reducing power consumption.
The LPDDR SDRAM supports clock stop under the following conditions:
the last command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has
executed to completion, including any data-out during read bursts; the number of clock pulses per access
command depends on the devices AC timing parameters and the clock frequency;
the related timing conditions (tRCD, tWR, tRP, tRFC, tMRD) has been met;
CKE is held High
When all conditions have been met, the device is either in “idle state” or “row active state” and clock stop mode
may be entered with CK held Low and
CK held High.
Clock stop mode is exited by restarting the clock. At least one NOP command has to be issued before the next
access command may be applied. Additional clock pulses might be required depending on the system
characteristics.
The following Figure shows clock stop mode entry and exit.
Initially the device is in clock stop mode
The clock is restarted with the rising edge of T0 and a NOP on the command inputs
With T1 a valid access command is latched; this command is followed by NOP commands in order to allow for
clock stop as soon as this access command is completed
Tn is the last clock pulse required by the access command latched with T1
The clock can be stopped after Tn
7.14.1 Clock Stop Mode Entry and Exit
Valid
NOP
CMD
NOP
Tn
T2
T1
T0
CK
CKE
Command
DQ,DQS
Timing
Condition
(High-Z)
= Don't Care
Enter Clock
Stop Mode
Valid
Command
Exit Clock
Stop
Mode
Clock
Stopped
Address
相关PDF资料 |
PDF描述 |
|---|---|
| W963B6BBN80E | 512K X 16 PSEUDO STATIC RAM, 75 ns, PBGA48 |
| W964A6BBN70E | 1M X 16 PSEUDO STATIC RAM, 65 ns, PBGA48 |
| W964L6ABN70E | 1M X 16 PSEUDO STATIC RAM, 65 ns, PBGA48 |
| W964L6ABN70I | 1M X 16 PSEUDO STATIC RAM, 65 ns, PBGA48 |
| W971GG6JB-25A | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W949D2KBJX5E | 制造商:Winbond Electronics Corp 功能描述:512M MDDR, X32, 200MHZ 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W949D2KBJX5I | 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W949D2KBJX6E | 制造商:Winbond Electronics Corp 功能描述:512M MDDR, X32, 166MHZ 制造商:Winbond Electronics Corp 功能描述:IC MEMORY |
| W949D6CB | 制造商:WINBOND 制造商全称:Winbond 功能描述:512Mb Mobile LPDDR |
| W949D6CBHX5E | 功能描述:IC LPDDR SDRAM 512MBIT 60VFBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:4G（256M x 16） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:0°C ~ 70°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP I 包装:Digi-Reel® 其它名称:557-1461-6 |
发布紧急采购，3分钟左右您将得到回复。