参数资料
型号: XC4VLX15-11FFG676I
厂商: XILINX INC
元件分类: FPGA
英文描述: FPGA, 1536 CLBS, 1205 MHz, PBGA676
封装: LEAD FREE, FBGA-676
文件页数: 24/58页
文件大小: 1863K
代理商: XC4VLX15-11FFG676I
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
30
Output Serializer/Deserializer Switching Characteristics
Table 36: OSERDES Switching Characteristics
Symbol
Description
Speed Grade
Units
-12
-11
-10
Setup/Hold
TOSDCK_D / TOSCKD_D
D input Setup/Hold with respect to CLKDIV
0.35
–0.05
0.42
–0.04
0.50
–0.03
ns
TOSDCK_T / TOSCKD_T(1)
T input Setup/Hold with respect to CLK
0.43
–0.16
0.52
–0.16
0.62
–0.16
ns
TOSDCK_T2 / TOSCKD_T2(1)
T input Setup/Hold with respect to CLKDIV
0.35
–0.05
0.42
–0.04
0.50
–0.03
ns
TOSCCK_OCE / TOSCKC_OCE
OCE input Setup/Hold with respect to CLK
0.45
0.01
0.53
0.02
0.64
0.03
ns
TOSCCK_S
SR (Reset) input Setup with respect to CLKDIV
0.67
0.80
0.96
ns
TOSCCK_TCE / TOSCKC_TCE
TCE input Setup/Hold with respect to CLK
0.45
0.01
0.53
0.02
0.64
0.03
ns
Sequential Delays
TOSCKO_OQ
Clock to out from CLK to OQ
0.41
0.49
0.59
ns
TOSCKO_TQ
Clock to out from CLK to TQ
0.41
0.49
0.59
ns
Combinatorial
TOSDO_TTQ
T input to TQ Out
0.56
0.65
0.76
ns
TOSCO_OQ
Asynchronous Reset to OQ
1.14
1.37
1.64
ns
TOSCO_TQ
Asynchronous Reset to TQ
1.14
1.37
1.64
ns
Notes:
1.
TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T / TOSCKD_T in TRCE report.
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XC4VLX15-12FFG676C FPGA, 1536 CLBS, 1205 MHz, PBGA676
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