参数资料
型号: XC4VLX15-11FFG676I
厂商: XILINX INC
元件分类: FPGA
英文描述: FPGA, 1536 CLBS, 1205 MHz, PBGA676
封装: LEAD FREE, FBGA-676
文件页数: 28/58页
文件大小: 1863K
代理商: XC4VLX15-11FFG676I
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
34
Table 41: FIFO Switching Characteristics
Symbol
Description
Speed Grade
Units
-12
-11
-10
Sequential Delays
TFCKO_DO
Clock CLK to DO output(2)
0.72
0.80
0.92
ns, Max
TFCKO_FLAGS
Clock CLK to FIFO flags outputs(3)
0.93
1.04
1.19
ns, Max
TFCKO_POINTERS
Clock CLK to FIFO pointer outputs(4)
1.16
1.29
1.48
ns, Max
Setup and Hold Times Before Clock CLK
TFDCK_DI / TFCKD_DI
DI input(5)
0.18
0.26
0.20
0.28
0.23
0.33
ns, Min
TFCCK_EN / TFCKC_EN
Enable inputs(6)
0.66
0.26
0.73
0.28
0.84
0.33
ns, Min
Reset Delays
TFCO_FLAGS
Reset RST to FLAGS(7)
1.32
1.46
1.68
ns, Max
Maximum Frequency
FMAX
FIFO in all modes
500.00
450.45
400.00
MHz
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
2.
TFCKO_DO includes parity output (TFCKO_DOP).
3.
TFCKO_FLAGS includes the following parameters: TFCKO_AEMPTY, TFCKO_AFULL, TFCKO_EMPTY, TFCKO_FULL, TFCKO_RDERR, TFCKO_WRERR.
4.
TFCKO_POINTERS includes both TFCKO_RDCOUNT and TFCKO_WRCOUNT.
5.
TFDCK_DI includes parity inputs (TFDCK_DIP).
6.
TFCCK_EN includes both WRITE and READ enable.
7.
TFCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT and WRCOUNT.
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